电光与控制, 2014, 21 (6): 99, 网络出版: 2014-06-24  

SDDR存储器: 新型存储架构设计

SDDR Memory:A New Type of Memory Architecture
作者单位
太原理工大学信息工程学院, 太原030024
摘要
迄今为止, SDRAM存储器的扩容完全依赖于半导体工艺水平的升级, 而提速取决于对时钟的利用方式。DDR3 SDRAM已达8倍速率, 再提速已很困难。提出一种新型串行访问的SDDR存储器结构和片内串行只写总线, 将DDR存储器封装成消息连接的构件, 将访问存储器的命令、地址和数据等信息打成消息报包, 经片内串行只写总线与构件化的DDR存储器交换信息。SDDR存储器减少了引脚, 连接简单并且抗干扰能力强、可靠性高, 易于扩容和进一步提升时钟速率, 具有明显的实用前景。
Abstract
So far SDRAM memory expansion is entirely dependent on the upgrade of semiconductor technology, and the speed-up is up to the clock utilization pattern.The speed of DDR3 SDRAM has been increased by a factor of 8, hence the further improvement is extremely difficult.A novel serial access SDDR memory structure and on-chip serial only write bus are presented in this paper, encapsulating the DDR memory into components connected by message, packaging such information of the accessed memory as command, address and data and so forth into message packet and exchanging information through on-chip serial only write bus and component-based DDR memory.SDDR memory reduces the number of pins, has simple connection, high anti-interference ability and reliability, and is easy for expansion and improving the clock rate further.Therefore, it has obvious practical prospects.

鲍丽娜, 张威, 张刚. SDDR存储器: 新型存储架构设计[J]. 电光与控制, 2014, 21(6): 99. BAO Li-na, ZHANG Wei, ZHANG Gang. SDDR Memory:A New Type of Memory Architecture[J]. Electronics Optics & Control, 2014, 21(6): 99.

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