高速傅里叶变换(FFT)处理器的设计是实时信号处理系统的核心问题。本文基于现场可编程门阵列FPGA(Field Programmable Gate Array),采用并行处理和单路延迟反馈SDF(Single-path Delay Feedback)流水线技术相结合的方法,设计了高速FFT处理器。该处理器内存资源消耗较并行结构有所减少,运算速度较单独的SDF流水线结构有所提高。建立了处理器的算法和设计模型,并根据模型对处理器各组成模块进行了优化设计,在保证处理器速度的同时,减小了资源消耗,其工作频率可以达到150 MHz,数据率超过600 Msps,软件仿真结果和实验室硬件平台测试验证了设计的可行性。

Design of a high-speed Fast Fourier Transform(FFT) processor is one of key points in a real time signal processing system.In this paper,a high speed and a hybrid architecture FFT processor combining a parallel processing with a Single-Path Delay Feedback(SDF) pipeline is designed based on Field Programmable Gate Array(FPGA) chip. Compared with the full parallel architecture,the memory cost of the designed processor decreases,thus the speed is higher than that of the SDF pipeline architecture. An algorithm and a design model for the processor are established and the three modules in the processor are optimized to decrease the resource cost greatly,thus the speed is higher than that of generous pipeline architectures.a verification is carried out with the FPGA simulations and hardware circuits’ platform in a lab,the results show that the operating frequency reaches 150 MHz and the data flow exceeds 600 Msps.