根据提升小波的框架结构,提出了基于FPGA小波变换核的设计与实现方案;根据自顶向下的设计思想,利用FPGA片内存储资源,实现了行列变换的并行执行;该结构由一个行处理器和一个列处理器组成,行、列处理器通过时分复用同时进行滤波,用优化的移位加操作替代乘法操作;采用流水线设计方法,减少了运算量,提高了硬件资源利用率;整个模块采用VHDL语言进行设计,并在QuartusⅡ下进行了编译和仿真。经验证系统工作可靠,完全满足实时处理的要求。

According to the framework of wavelet transform,a method for wavelet transform kernel design was proposed based on FPGA. According to top-down design philosophy,the whole architecture took full advantages of the memory bits in FPGA,which made row and column processors work in parallel. It consisted of one row processor and one column processor,and the two processors performed filtering in parallel by time multiplexing. Optimized shift-add operations were substituted for multiplications,and edge extension was implemented by embedded extension algorithm. Pipeline design was used to decrease calculation cost and improve hardware operation efficiency. VHDL language was adopted for module design,the compilation and simulation were made under QuartusⅡ.Experiment verified the reliability of the architecture,which can satisfy the requirement of real-time processing.