开发了一种新型的帧存储像素电路结构，实现了像素内低功耗。通过SPICE仿真对新型像素结构的工作时序和功耗进行了验证。本像素结构通过像素内嵌电压比较器对相邻两场数据电压进行比较来实现帧存储像素电路放电操作的智能控制，这种智能放电操作降低了LCoS的功耗。

A novel frame buffer pixel circuit was developed which acquires low power inside a pixel. The function timing and power of this novel pixel circuit was evaluated by SPICE simulation. A voltage comparator embedded in a pixel compares the adjacent frame data voltage by which the intelligent discharge operation was realized. This intelligent discharge operation lowers the power dissipation in LCoS backplane.