文章采用0.25 μm互补型金属氧化物半导体( CMOS)工艺设计了一种622 Mbit/s速率光接收模块的限幅放大器，整个系统包括偏置电路、输入缓冲、三级放大、输出缓冲和直流反馈，采用全差分结构。利用3.3 V电源供电，功耗约为109 mW，电路增益可达97 dB，在46 dB的输入动态范围内可以保持790 mV的恒定输出摆幅。

A limiting amplifier for 622 Mbit/s optical receiver module is designed by adopting the 0.25 μm CMOS technology. In a fully differential structure, the whole system consists of a bias circuit, an input buffer, three similar amplifier cells, an output buffer and a DC feedback. With a 3.3 V power supply, its power dissipation is about 109 mW, its circuit gain reaches 97 dB and it maintains a constant output voltage swing of 790 mV in an input dynamic range of 46 dB.