介绍了中国散裂中子源/快循环质子同步加速器射频同步相位环路的数字化控制系统设计方案, 并利用ALTERA公司的现场可编程门阵列开发面板进行了系统开发, 完成了控制回路的编程与仿真, 进行了桌面实验和低功率实验, 并对其进行了分析与讨论。实验结果表明: 同步相位环路运行稳定, 控制误差小于1°, 满足物理设计要求。

The RF phase control loop of the rapid cycling synchrotron (RCS) of China spallation neutron source (CSNS) is designed with an FPGA-based digitalized control system. It should be able to control the RF phase to follow the beam synchronous phase when the RF frequency is rapidly sweeping during the acceleration, which is important for the rapid acceleration and the stabilization of the beam during the acceleration cycle and for the minimization of the beam loss level. This paper presents the design and the experiments of the phase control loop system which uses an FPGA development board from ALTERA Co..Both the desk experiments and the low-power ones with an assembled RF system show that, the phase control loop can run stably with the control error smaller than 1°, satisfying the design requirement.