文章讨论了在数字通信系统中RS码的Step-by-step译码算法，给出了算法的基本原理并在现场可编程门阵列(FPGA)上实现了RS (7,3) 码的编译码，给出了实际仿真的效果图。结果表明，所设计的电路能够纠正7 位接收符号中的任意两位错误。采用此算法避开了求解错误定位多项式，使译码过程得以简化，并提高了译码速度，且易于用大规模可编程器件实现。

This article discusses the Step-by-step decoding algorithm for the RS code in the digital communication system, gives its the basic principle and realizes the RS (7,3) code on FPGA, and the actual simulation effect chart. The result indicates that the designed electric circuit can correct any two errors in 7 received marks. As the solution of erroneous localization multinomial by using this algorithm, the decoding process can be simplified and decoding speed increased, facilitating the realization of large-scale programmable components.