半导体光子学与技术, 2005, 11 (1): 12, 网络出版: 2011-08-18
Analysis and Implementation of Traffic Buffering in EOS Chip Design
Analysis and Implementation of Traffic Buffering in EOS Chip Design
摘要
Abstract
The traffic buffering problems in the ethernet over synchronous digital hierarchy(EOS) are introduced and analyzed. Different solutions are also presented in detail. Synchronous DRAM(SDRAM) is used as off-chip buffer to store-and-retransmission ethernet frames. A new and easy control design is introduced here. The buffer area size on chip is greatly reduced and the power dissipation is lowed at the same time.
FENG Bo, LIU Hao, YIN Yan-fen. Analysis and Implementation of Traffic Buffering in EOS Chip Design[J]. 半导体光子学与技术, 2005, 11(1): 12. FENG Bo, LIU Hao, YIN Yan-fen. Analysis and Implementation of Traffic Buffering in EOS Chip Design[J]. Semiconductor Photonics and Technology, 2005, 11(1): 12.
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