主要介绍了低介电常数介质芯片层间介质层的分类, 特别是对铜线键合过程中低介电常数介质层间介质断层方面的分析, 以及铜线键合过程中如何优化工艺。在工艺优化过程中主要采用了键合参数的优化来改善芯片本身存在的设计缺陷, 这主要是从工艺稳定性方面考虑。通过一系列工艺的优化, 通过大量实验设计, 获得了尽可能少的层间介质断层缺陷。

The classifications of inner layer dielectric (ILD) layers of dielectric chips with low dielectric con. stant (Low K) are introduced. During copper wire bonding, ILD crack layer of the dielectric with low K and optimi. zation process are analyzed. Considering techniques stability, optimization bonding parameters are adopted to im. prove the design shortcomings of chips during optimization process. After a series of techniques optimization and plenty of experiment designs, the minimum ratio of ILD crack layer has been achieved.