为研究槽缝型缺陷参考平面对高速信号的影响，主要基于场路混合仿真，使用三维全波方法提取槽缝缺陷参考平面参数，并结合电路仿真，分别对单端微带线与耦合微带线跨越不连续参考平面的影响进行分析，讨论了这些影响是如何作用于高速数字系统的时序与噪声，并引入眼图予以说明。仿真结果表明开槽长度与宽度都会增大信号回路电感，信号上升沿时间会随着返回路径的增加而退化，从而引起高速数字系统时序抖动，耦合微带线间的串扰随返回路径增加而急剧增加，在抖动与噪声的共同作用下，会对系统数据接收到的信号产生破坏性作用，在高速PCB设计中应遵从使返回路径最小的原则，避免共同的信号返回路径是关键。由此总结出降低不完整参考平面高速互连线间耦合及串扰的设计规则。

To assess the impacts of the slotted defect reference plane on high speed signal propagation, the analysis was carried out based on hybrid fieldcircuit approach which incorporates 3D fullwave and circuit simulations to analyze the effects of single ended microstrip line and coupling microstrip lines across slotted defect reference plane respectively. And the mechanisms of these effects acting on the jitter and noise of high speed digital system were discussed; moreover, the eye diagrams were introduced to make description. The simulation results show that the signal loop inductance increases with both the length and width increasing of the slot, the signal rise time degenerates with the increase of return path, then the jitter of the system increases. Crosstalk between coupled microstrip lines increases sharply according to the increase of signal return path. It will cause a devastating impact on system data transfer under the interaction of jitter and noise. Therefore, reducing the signal return path and keeping the reference plane complete are the key to achieve a good signal quality. In addition, the common signal return path should be avoided.