针对基于光传送网的数据分组交换技术中ODU（光信道数据单元）切割过程中如何将缓存中的位宽为64位的ODU2按照要求以任意1～8个字节取出的问题，用自顶向下的设计方法设计了一种自适应的数据拆分和重排电路结构，并用Verilog硬件描述语言实现了该结构，同时进行了功能仿真和逻辑综合。结果表明，该数据顺序重排结构的工作频率可以达到280 MHz，能够显著提高ODU切割为数据包的效率。

For the purpose of extracting any 1～8 bytes as required from the 64bit ODU2 data stream stored in the buffer memory in the course of ODU2 segmentation in the OTNbased data packet switching technology, an adaptive ODU2 data splitting and rearrangement circuit structure is designed in a topdown way and implemented by using VerilogHDL and the function simulation and logic synthesis are conducted. The results show that the data splitting and rearrangement structure can operate at up to 280 MHz, significantly improving the efficiency of ODU2 data flow cutting.