为校准流水线模拟数字转换器(ADC)中电容失配和由运算放大器的有限开环增益引起的级间增益误差, 提出了一种新的基于权重的后台校准技术。该技术将流水线ADC中存在的上述误差统一归结为各级权重的偏差, 建立了一个基于权重的ADC误差模型, 并利用后级的数字输出来校准前级的误差。该技术在ADC末尾增加了额外的两个子级, 这两个子级仅在校准过程中使用, 从而使得ADC正常的模数转换过程不被中断, 校准进程在后台执行。由于在校准期间和正常工作期间所有可能出现的信号路径的前7级均被校准, 故进一步减小了误差, 提高了精度。应用该技术实现了一个14 bit, 80 MS/s的流水线ADC, 该芯片采用Chartered 0.18 μm, 1p6m CMOS工艺设计, 总功耗为260 mW, 芯片面积为7.161 mm2。实验结果显示: 本文提出的校准技术可以提高ADC的精度, 改善ADC的动态和静态性能。

To reduce and eliminate the interstage gain errors caused by capacitor mismatch and finite open-loop gain of an operating amplifier in a pipelined Analog to Digital Converter (ADC), a novel weight-based calibration technique on backend stages was presented. With proposed technique, a weight-based error model was built by merging error factors into a single term and the outputs of backend stages were utilized to calibrate the errors of front stages. To avoid interrupt normal conversion process, two extra stages were used in the calibration process to implement background calibration. During the normal conversion process and calibration process, the first seven stages of every signal path were all calibrated to increase the resolution and to eliminate errors. The improved technique was used in the implementation of 14 b, 80 MS/s pipelined ADC, and the ADC is with Chartered 0.18 μm, 1p6m CMOS process, a consume of 260 mW, and a chip area of 7.161 mm2. The test results show that the calibration technique improves dynamic and static performance and increases the precisions of pipelined ADCs.