为了Camera Link摄像机的小型化和集成化,设计并实现了基于FPGA的Camera Link接口的编码输出功能.输出编码分为3个步骤:首先,完成图像像素数据到Camera Link PORT的映射;其次,根据DS90CR287的数据编码要求对PORT数据和同步时钟信号进行编码;最后,通过FIFO和并串转换功能模块完成图像数据和时钟编码信号的LVDS信号输出.使用ModelSim软件,对像素时钟为40 MHz的BASE模式进行了仿真,同时在实物实验中,完成了像素时钟为40 MHz的FULL模式的实验,通过以上两方面实验验证了设计的Camera Link输出编码方案的正确性和可行性.提出的编码方案稳定可靠,可以应用于不同模式下的Camera Link编码输出,具有很高的灵活性和应用价值.

In order to miniaturize and integrate Camera Link camera,an output-encoding function based on Camera Link interface was designed and implemented.The implementation is divided into three steps:firstly,mapping image pixel data to the Camera Link PORT;secondly,encoding the PORT data and synchronous clock signal according to the data coding requirements of DS90CR287;finally,completing the LVDS output which contains the image data and clock signal through FIFO and parallel-to-serial conversion module.The BASE model that the pixel clock is 40 MHz was emulated using ModelSim,at the same time,the FULL model that the pixel clock is 40 MHz was experimented.The experimental results demonstrate the correctness and feasibility of the Camera Link output encoding scheme.The proposed coding scheme is stable and reliable,it can be used in different modes,with high flexibility and practicability.