通过分析流水线数字转换器(ADC)中参考电压缓冲器的工作过程，提出了相应的负载模型，并推导出缓冲器的指标，设计了一种能用于高速高精确度流水线ADC的参考电压缓冲器。该缓冲器采用了改进的开环结构，降低了设计复杂度、功耗和面积，同时采用增强型源跟随结构，提高了缓冲器驱动能力和稳定性。该参考电压缓冲器采用华力55 nm CMOS工艺进行电路和版图设计，版图面积为320 μm×260 μm。Spectre后仿真结果表明，参考电压缓冲器功耗为3 mA，建立时间为4.3 ns，成功应用于60 MS/s 12 bit流水线ADC。

The load model and the index requirements are proposed through analyzing the working process of reference buffer in pipelined Analog to Digital Converter(ADC) in the paper. Finally a reference buffer used in high-speed high-precision pipelined ADC is designed. The buffer adopts an improved open loop structure to induce design complexity，power consumption and area. Moreover an enhanced source follower structure is used to improve driving capability and stability. The design of schematic and layout is based on Huali Microelectronics Corporation(HMLC) 55 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology，and layout area is 280 μm×240 μm. The post simulation result shows that the power of buffer is 3mA and the setting time is 4.3 ns. The buffer can be used in 60 MS/s 12 bit pipelined ADC.