基于0.13 μm SiGe BiCMOS工艺,研究和设计了一种D波段功率放大器芯片。该放大器芯片用了四个功率放大器单元和两个T型结网络构成。功率放大器单元采用了三级的cascode电路结构。低损耗的片上T型结网络既能起到片上功率合成/分配的功能,又能对输入输出进行阻抗匹配。对电路结构进行了设计、流片验证和测试。采用微组装工艺将该芯片封装成为波导模块。小信号测试结果表明：该功放芯片工作频率为125~150 GHz,最高增益在131 GHz为21 dB,最低增益在150 GHz为17 dB,通带内S22小于-7 dB,S11小于-10 dB。大信号测试结果表明：该功放模块在128~146 GHz带内输出功率都大于13 dBm,在139 GHz时,具有最高输出功率为13.6 dBm,且1 dB压缩功率为12.9 dBm。

This paper presents D-band SiGe power amplifier(PA) developed by using the 0.13 μm SiGe BiCMOS technology. Building blocks of a 4-way amplifier are implemented using three-stage cascode power amplifier units, and T-junction networks are used for power combining and splitting. The PA chip works in 125-150 GHz, and achieves a small-signal biggest gain of 21 dB at 131 GHz, with a small-signal lowest gain of 17 dB at 150 GHz. The PA module exhibits a saturated output power of 13.6 dBm and an output 1 dB gain compression power of 12.9 dBm at 139 GHz.