为了减小频域均衡系统电路实现的功耗和面积, 满足长距离少模光纤通信对均衡器的要求, 对关键环节快速傅里叶变换（FFT）电路的实现进行了研究, 采用2维分解算法将大点数的FFT运算转换为小点数FFT处理器的设计, 降低了硬件复杂度。设计了基于现场可编程门阵列的高速蝶形运算核, 实现了16384点FFT的2维R22SDF结构, 提高存储器的资源利用率, 减少了复数乘法器的使用; 进行了理论分析和实验验证, 取得了不同时钟频率下的电路结构占用资源的数据。结果表明, FFT运算器的正确性得到验证, 该FFT运算器能够适应少模光纤通信系统中优化频域均衡电路结构的要求, 能够实现200MHz数据传输速度的频域均衡实时处理。

To reduce the circuit’s power and size of frequency domain equalization (FDE) system, and meet the requirements of FDE in long-distance few-mode fiber communication, the circuit for fast Fourier transformation (FFT), the key of FDE, was studied. The long point FFT operation was converted to short FFT by means of 2-D decomposition algorithm, and the hardware complexity was reduced. High-speed butterfly core based on field-programmable gate array(FPGA) was designed to implement 2-D R22SDF structure of 16384 point FFT, improve the resource utilization of memory and reduce the usage of complex multipliers. Through theoretical analysis and experiments, resource consumption information of the circuit under different clock frequencies was collected. The result show that the designed FFT can satisfy the optimization requirement of FDE circuit structure in few-mode fiber communication and realize real-time processing of 200MHz data speed in FDE.