扩展计数（ extended counting）模数转换器（ ADC）合并了 Sigma-Delta(..) ADC的高精度和奈奎斯特率 ADC的高速低功耗优势，具有中高精度和中等的转换速度，在图像传感器方面具有很好的应用前景。以 ΣΔADC与逐次逼近（ SAR） ADC的组合结构的扩展计数 ADC为例，基于 0.35 .m的 CMOS工艺，对其进行了电路层面的设计。通过电路级仿真验证了该工艺下 ADC的功能并且得到了部分的性能参数。

The extended counting analog-to-digital converter (ADC) combines the accuracy of ΣΔADC and the speed and power consumption of Nyquist-rate ADC. It has a good application foreground for its high resolution with a medium conversion speed. The combination of ΣΔADC and successive approximation register (SAR) ADC has been chosen as the structure of extended counting ADC, and the extended counting ADC has been designed and simulated based on the 0.35 .m CMOS technology. The extended counting ADC has been verified and some properties have been given by the simulation.