提出了一种基于半监督自适应增强 (AdaBoost)模型树的建模方法，用于现场可编程门阵列(FPGA)的性能表征。该方法以半监督学习方式，构建了 FPGA性能关于 FPGA架构参数的解析模型，同时采用 AdaBoost算法提高 FPGA性能模型的预测精确度。使用 VTR(Verilog To Routing)电路集，基于该方法构建的性能模型在预测 FPGA上实现的应用电路面积时，平均相对误差( MRE)为4.42%; 预测延时的MRE为1.63%; 预测面积延时积时，MRE为5.06%。与全监督模型树算法以及现有的半监督模型树算法相比较，该方法构建的 FPGA实现面积模型的预测精确度分别提高了 39%,26%。实验结果显示，该方法在确保较少的时间开销前提下，构建了具有高预测精确度的 FPGA性能模型，提供了一种高效的 FPGA性能表征方法。

A semi-supervised Adaptive Boosting(AdaBoost) model tree based modeling approach is proposed for Field Programmable Gate Array(FPGA) performance characterization. The proposed approach, which adopts AdaBoost to improve the prediction accuracy, constructs an analytical performance model with regard to the FPGA architecture parameters in semi-supervised learning way. The FPGA performance model built through the proposed approach estimates the area, delay and area-delay product with Mean Relative Errors(MREs) of 4.42%, 1.62% and 5.06%, respectively. Compared to the supervised model tree and the previous semi-supervised model tree algorithm, the proposed approach boosts the estimation accuracy by 39% and 26% respectively. Experimental results show that the proposed approach is proved to be an efficient FPGA characterization approach, building FPGA performance models with high accuracy in less time cost. The proposed modeling approach can be applied to explore the FPGA architecture design space effectively and efficiently.