介绍了一种改进的流水线模数转换器(ADC)数字校准算法，该算法使用了一个低速高精确度的参考ADC，同时结合了变步长的最小均方误差(LMS)滤波器校正流水线ADC 的误差，从而提高校准速度和精确度。使用Verilog HDL 语言设计了这种后台数字校准算法的寄存器传输级(RTL)电路，同时采取Simulink 和Modelsim 联合仿真的方法对电路进行验证。验证结果表明，与固定步长的校准算法相比，改进的校准算法拥有更快的收敛速度和更高的收敛精确度。

An improved digital backstage calibration algorithm to calibrate high-speed pipeline Analog to Digital Converter(ADC) is introduced. This algorithm combines the slow but accurate ADC as a reference with an adaptive filter based on Least Mean Square(LMS) algorithm to rectify errors of the pipeline ADC, thereby improving the speed and accuracy of the calibration. The Verilog HDL is used to design the Register Transfer Level(RTL) circuit. At the same time, the co-simulation method of Simulink and Modelsim is adopted to verify the circuit. The verification result shows that the improved calibration algorithm has better convergence speed and accuracy compared with that of fixed-step calibration algorithm.