针对存储转发系统数据随机性、不同接口之间时序异步的特点, 提出了不同于典型平台的事物级数据结构和参考模型设计, 构建基于 System Verilog语言的通用验证方法学 (UVM)的验证平台。验证结果表明, 此验证平台能够灵活控制随机约束和验证进程, 优化验证事务。该平台提高了验证的效率和验证平台的可重用性, 较好地满足了超大规模可编程逻辑器件验证需要。

For the storage and retransmission systems, aiming at the characteristics of randomness of data and asynchronization with different interfaces, a kind of transaction-level data structure and a reference model are presented which are different from the typical verification platform. A so-called Universal Verification Methodology(UVM)-based System Verilog verification platform is built. According to the results of verification, both the random constraint and verification process can be controlled flexibly. The test bench and test cases are optimized. This platform can improve the verification efficiency and platform reusability. It well meets the requirements of verification of very large scale programmable logic devices.