提出了一种连续速率的时钟数据恢复 (CDR)电路, 可覆盖 500 Mbps到 4 Gbps数据率。该 CDR电路在 130 nm互补金属氧化物半导体 (CMOS)工艺下实现, 基于相位插值 (PI)原理, 采用数字投票电路和相位控制逻辑替代电荷泵和模拟滤波器以方便工艺移植。为缩小片上锁相环 (PLL)输出时钟频率范围, 同时避免 PI电路处于非线性区, 该 CDR电路采用多种速率模式切换的方式将采样时钟频率限定在 500 MHz~1 GHz之间。 PI电路为 7 bit精确度, 线性度良好, 4 Gbps数据率时, 恢复时钟的峰峰值抖动约为 25.6 ps。该 CDR误码率在 10-10以下, 可跟踪昀大 ±976.6 ppm的数据频偏, 功耗约为 13.28 mW/Gbps, 测试芯片大小为 5 mm2, 其中 CDR芯核部分为 0.359 mm2。

A continuous-rate Clock Data Recovery(CDR) circuit is proposed, which covers a data rate of 500 Mbps to 4 Gbps. The proposed CDR, implemented in 130 nm Complementary Metal Oxide Semiconductor(CMOS), is based on phase interpolation and utilizes digital voter and phase control logic instead of charge pump and analog filter, which is meaningful to transplantation between different technologies. To reduce the frequency range of the clock of Phase Lock Loop(PLL) outputs and avoid the Phase Interpolator(PI) getting into the nonlinear region, multimode is designed to limit the frequency range of the sampling clock only from 500 M to 1 GHz. The PI realizes an accuracy of 7 bit and a good linearity, while the peak-to-peak jitter of the recovered clock of is about 25.6 ps at 4 Gbps. The CDR realizes a BER<10-10 and is able to track a maximum frequency offset of ±976.6 ppm between the input data and the sampling clock. The power consumed by the proposed CDR is 13.28 mW/Gbps. A 5 mm2 test chip is also fabricated, where the CDR core occupies 0.359 mm2 of area.