提出了一种支持可变位宽高效加法的现场可编程逻辑门阵列(FPGA)嵌入式数字信号处理(DSP)单元知识产权(IP)硬核结构, 相比于Altera公司的Stratix-III DSP结构, 基于本文提出的优化结构可以更高效地实现加法、乘加以及累加等多种应用。利用软件对不同数据类型和位宽的输入实现数据预处理, 减小了硬件资源的开销, 并进一步提升了电路性能。同时在DSP结构中加入了乘法旁路器和二级符号位扩展的加法电路, 在减小DSP实现面积的同时, 支持超高位宽、高速的流水线型加法运算, 扩展了DSP的应用范围。采用TSMC 55 nm标准CMOS工艺设计并完成了所提出的DSP IP核的电路实现, 可实现包括72位可变位宽加法及36位可变位宽乘法等在内的9种运算模式。

An embedded Field-Programmable Gate Arrays(FPGA) Digital Signal Processor(DSP) core's architecture which supports efficient width variable addition is presented. Compared with the Stratix-III DSP core of Altera corporation, the optimized architecture will give higher efficiency to a variety of applications such as addition, multiply-addition and accumulation. It can not only reduce the circuit area but also improve the circuit performance by using software to pre-process the data with different types and bit-width. Meanwhile, a multiply-bypass circuit and two-stage sign extensional addition circuit are added to the DSP core, which implements a high bit-width, high-speed pipelined operation and reduces the circuit area as well. The design of DSP IP(Intellectual Property) core utilizes TSMC 55 nm CMOS technology, which supports nine-operation modes including 72 bit addition and 36 bit multiplication for variable width inputs.