系统级静电放电(ESD)效应仿真可以在电子系统进行测试之前进行有效的静电放电效应防护, 缩短研发周期。根据传输线脉冲测试(TLP)结果, 对瞬态电压抑制(TVS)二极管和芯片引脚进行spice行为建模, 结合ESD脉冲源的等效电路模型, PCB板的S参数模型, 采用场路协同技术完成了系统级静电放电效应的仿真。针对一个典型的电子系统, 在IEC 61000-4-2 ESD应力作用下, 完成了一款开关芯片防护电路的仿真, 并对电路进行了加工、放电测试, 仿真与测试芯片引脚的电压波形吻合良好, 验证了该仿真方法的有效性。

Effective protection can be conducted before an electronic system is measured through system-level ESD simulation. In this paper, the spice behavioral modeling for the transient voltage suppressor and IC pins are presented using the measured transmission line pulse (TLP) data. A system-level ESD simulation methodology is proposed, including the equivalent circuit model of ESD pulse source, S-parameter model of PCB board, TLP model of TVS protection diode, IC pins and co-simulation technology. A switch chip protect circuit is simulated and measured under IEC 61000-4-2 ESD stress. The good agreement between simulated and measured voltage waveforms demonstrates the effectiveness of the proposed simulation method.