在同步数字体系(SDH)中, 定位过程中的指针调整会使输出信号产生较大的抖动, 为保证信号的质量, 提出一种用于SDH中E1支路接收端的去同步电路。该电路由自适应滤波器和中等带宽的二阶数字锁相环(PLL)组成。PLL中的数控振荡器由串行累加器和双模分频器组成, 采用鉴频鉴相并置的方法, 并使用了数字滤波器。通过建立数学模型, 对其工作过程及输出抖动进行分析。实验结果表明其性能指标可以满足ITU-T的相关标准。

In synchronous digital hierarchy(SDH) , pointer adjustment during positioning will cause great jitter of output signal. In order to ensure the quality of signal, a de-synchronization circuit which is used in the receiving end of E1 tributary in SDH is proposed. The circuit contains an adaptive filter and a second-order digital phase-locked loop(PLL) with medium bandwidth. The numerical control oscillator in PLL consists of a serial accumulator and a dual-mode divider. It adopts the method of frequency discrimination and phase discrimination in parallel, and uses a digital filter. By establishing mathematical model, its working process and output jitter are analyzed. Simulation results show that the performance index meets the related standard of ITU-T.