太赫兹科学与电子信息学报, 2020, 18 (3): 491, 网络出版: 2020-07-16  

面向 eFPGA的拼接式布线资源建模方法

Module-based routing resource graph modeling of eFPGA
作者单位
1 中国科学院大学,北京 100049
2 中国科学院电子学研究所,北京 100190
摘要
嵌入式可编程门阵列核 (eFPGA)在定制过程中的每一次迭代,都需要在新生成的布线资源图(RRG)上进行布线,进而完成该次迭代对面积 /时序等参数的评估。传统的 eFPGA RRG建图方法,在每次评估迭代时都需要 重新生成全芯片的结构描述并在其基础上建立布线边和布线点,建图问题复杂度随芯片规模线性增大,很容易达到性能瓶颈。为了应对上述挑战,首先针对复用单元类型建立其 RRG模型以及互连关系模型,然后采用一种根 据资源排布关系,以动态拼接方式即时生成不同待评估阵列规模 RRG的方法。实验证明,其相较于传统方法,在复用单元类型库不变的 eFPGA评估过程中,依赖更小且近乎不变的数据库,建图总时间降低了约 84%,内存峰 值占用平均降低了约64%,从而提高了 eFPGA的评估效率。
Abstract
During each iteration of embedded Field Programmable Gate Array(eFPGA) customization process, router has to be run on a new Route Resource Graph(RRG) for the new architecture in order to meet design constraints in many aspects, such as area and timing. Conventional eFPGA RRG modeling method regenerates the whole chip’s architecture description and builds routing nodes and edges based on it in every evaluation iteration. However, the efficiency of this method suffers from the rising scale of the chip being evaluated. A module-based RRG modeling method is proposed to address this problem. It firstly builds RRG for every module type and models interconnect relations among them, after that, stitches them together according to the device resource arrangement. It depends on a relatively small database, reduces the modeling runtime and memory peak footprint by around 84% and 64% respectively and thereby improves the eFPGA evaluation efficiency.

涂开辉, 王鑫楠, 黄志洪, 杨海钢. 面向 eFPGA的拼接式布线资源建模方法[J]. 太赫兹科学与电子信息学报, 2020, 18(3): 491. TU Kaihui, WANG Xinnan, HUANG Zhihong, YANG Haigang. Module-based routing resource graph modeling of eFPGA[J]. Journal of terahertz science and electronic information technology, 2020, 18(3): 491.

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