针对相位敏感光时域反射计(Φ-OTDR)信号处理复杂、计算量大、实时性要求高的特点,提出一种基于现场可编程门阵列(FPGA)异构加速计算技术的Φ-OTDR实时信号处理系统。对外差探测式Φ-OTDR信号处理流程进行分析与分解,提出基于FPGA的滑动窗数据帧分割、多通道并行快速傅里叶变换(FFT)计算、频域滤波、短时能量求和等一系列加速计算方法。该系统最终实现在40 km光纤传感距离、2 kHz重复频率与1 m采样间隔下的长时间、实时扰动信号解调与显示,并且具有80%的帧重叠率。该FPGA系统作为异构加速器,能够减轻计算机数据处理压力,保证传感系统高重复频率下的运算实时性,为系统可靠性和稳定性提供了有效保障。

A real-time phase-sensitive optical time-domain reflectometry (Φ-OTDR) signal processing system is proposed based on the heterogeneous accelerated computing technology of field programmable gate array (FPGA) with respect to the characteristics of complexity, large-amount computation, and high real-time requirements of the Φ-OTDR signal processing system. Firstly, the heterodyne-detection-type Φ-OTDR signal processing flow is analyzed and decomposed. Subsequently, a series of accelerated computing methods based on FPGA, such as sliding window data frame segmentation, multichannel parallel fast Fourier transform calculation, frequency-domain filtering, and short-term energy summation, are proposed. Finally, the system implements long and real-time disturbance signal demodulation and display using a fiber sensing distance of 40 km, a repetition rate of 2 kHz, and a sampling interval of 1 m with a frame overlap of 80%. The FPGA system acts as a heterogeneous accelerator to mitigate the computer data processing pressure and ensure real-time operation of the sensing system at a high repetition frequency, effectively ensuring the system reliability and stability.