设计了一款基于延迟锁定环(DLL)和同步计数器结构的10位片上时间数字转换电路(TDC)。采用两步层级设计方法, 利用同步计数器进行粗量化输出6位二进制码, 量化时钟周期的整数倍, 再利用高性能差分DLL输出16路固定相移的时钟信号采样, 精量化不足一个时钟周期的部分, 输出4位温度计码。该结构可以提供较好的精度、动态范围以及转换速度, 与传统的子门延时TDC相比, 该结构TDC占用的芯片面积更少, 转换速度更高, 受工艺、电压及温度影响更少。仿真结果表明: 该TDC 具有LSB 62.5 ps和MSB 64 ns的动态范围,满足一般与时间相关的单光子计数需要。

A 10 bits on-chip time-digital-converter(TDC) based on delay-locked-loop(DLL) and synchronized counter structure was designed. In two-step hierarchical way, synchromized counter generates 6 bits code which quantize coarsely the integral multiple of clock cycle, and a high performance differential DLL was adopted, which outputs 16 fixed-phase-shift clock to quantize finely the residue smaller than a clock cycle, with 4 bits thermometer code. This structure can provide better time resolution, dynamic range and conversion speed. Compared with traditional sub-gate delay TDC, it costs less area and converts faster, and is immuned from process, voltage and temperature changes. Spectre simulation results show its dynamic range of LSB @62.5 ps and MSB 64 ns, which is suitable for the time-correlated single photon counting(TCSPC) applications.