基于GaAs肖特基二极管, 设计实现了310~330 GHz的接收机前端.接收机采用330 GHz分谐波混频器作为第一级电路, 为降低混频器变频损耗, 提高接收机灵敏度, 分析讨论了反向并联混频二极管空气桥寄生电感和互感, 采用去嵌入阻抗计算方法, 提取了二极管的射频、本振和中频端口阻抗, 实现了混频器的优化设计, 提高了变频损耗仿真精度.接收机的165 GHz本振源由×6×2倍频链实现, 其中六倍频采用商用有源器件, 二倍频则采用GaAs肖特基二极管实现, 其被反向串联安装于悬置线上, 实现了偶次平衡式倍频, 所设计的倍频链在165 GHz处输出约10 dBm的功率, 用以驱动330 GHz接收前端混频器.接收机第二级电路采用中频低噪声放大器, 以降低系统总的噪声系数.在310~330 GHz范围内, 测得接收机噪声系数小于10.5 dB, 在325 GHz处测得最小噪声系数为85 dB, 系统增益为(31±1)dB.

A 310~330 GHz receiver front-end with Schottky diode was designed and tested. The receiver first stage is a subharmonic mixer (SHM). In order to lower conversion loss (CL) and improve receiver sensitivity, the diode parasitic parameters such as the air-bridges inductance and their mutual inductance were discussed. The diode RF, LO and IF port impedance were calculated with embedding analysis for circuit optimization. The simulated CL accuracy was improved. The LO sources was realized by a ×6×2 multiplying chain, in which the sextupler is a commercial active multiplying chip. The balanced doubler was realized by a anti-series Schottky diode mounted on a suspended line. The chain can generate 10 dBm output power at 165 GHz to pump the receiver SHM. The receiver second stage is a low noise IF amplifier for lowering system noise figure. In the frequency range of 310~330 GHz, the measured receiver noise figure is lower than 10.5 dB with a minimum value of 8.5 dB at 325 GHz. The receiver gain is (31±1) dB.