遥感设备需要配备高精度的本地时钟源与卫星平台时钟同步,数字锁相环设计是时钟同步和倍频的关键技术,而长周期输入信号和大倍频系数从两方面增加了设计难度。 设计了一种针对秒脉冲同步和10000倍倍频条件下的数字锁相环,通过建立Z 域模型和S域近似分析了其响应特性,用现场可编程门阵列予以实现。实验表明,本设计实现的数字锁相环最短可以在5个输入时钟 周期内进入锁定状态,稳定工作时每秒累积误差小于0.1 ms,在实际应用中可以稳定输出本地时钟,满足遥感设备时钟同步和倍频的需求。

The remote sensing equipment needs to be equipped with a high precision local clock source in order to synchronize with the clock of the satellite platform. The digital phase locked-loop design is a key technology of synchronization and frequency multiplication of the clock. Long period input signals and large frequency multiplication coefficient add more difficulties of the loop design from two different ways. Under the condition of second pulse synchronization and 10000 times frequency multiplication, a method of digital loop parameter algorithm was proposed. The response characteristics of the loop were analyzed by establishing the Z domain model and the approximate S domain model. The whole design was implemented by field programmable gate array. Experiments show that the design of the digital phase-locked loop can be locked in 5 input clock cycles, and the cumulative error is less than 0.1 ms per second during stable operation. In practical application, the digital phase locked loop can stabilize the output of the local clock to meet the needs of the remote sensing devices’ clock synchronization and frequency multiplication.