Author Affiliations
1 School of Physics and Microelectronics, Zhengzhou University, Zhengzhou 450001, China
2 Engineering Research Center for Semiconductor Integrated Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China
3 Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100083, China
4 Institute of Intelligence Sensing in Zhengzhou University, Zhengzhou 450001, China
We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO2 interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 1012 cm–2 and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.
Journal of Semiconductors
2022, 43(5): 054101
郑州大学物理工程学院, 河南 郑州 450000
激光器 表面等离子激元 混合表面等离子体波导 回音壁模式 
2019, 56(20): 202409

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