针对静态随机存取存储器(SRAM)型现场可编程门阵列(FPGA)位流码配置问题，提出一种自动配置互连资源的方法。该方法从描述FPGA 结构的行为级Verilog 文件中，采用基于端口映射的记忆FPGA 配置模型搜索(MCMS)算法自动提取互连资源的配置位模型，然后结合布线结果生成布线路径上互连资源的位流码。实验结果表明，对于包含30 Mb 配置位的3 000 万门SRAM型同质FPGA，采用人工方法提取互连资源配置位模型需要6 天时间，而采用端口映射MCMS 算法仅需要29 分钟，效率提高了298 倍；对于同等规模的异质FPGA，采用人工方法需要7 天时间，而采用端口映射MCMS 算法仅需26 分钟，效率提高了394 倍。该算法作为一种通用的互连资源配置位模型提取方法，可以应用于不同的FPGA 芯片。在缩短位流码配置时间的同时，提高位流码配置的准确性。

A Memorized Field Programmable Gate Array(FPGA) Configuration Model Search(MCMS) algorithm is presented to automatically generate configuration bitstream of routing resources to solve the bitstream configuration problem commonly existing in Static Random Access Memory(SRAM) FPGA. The main objective is to reduce the time for generating configuration bitstream of routing resources and improve the correctness of configuration process. This is achieved by allowing the MCMS algorithm to extract the model of configuration bitstream from the behavioral Verilog HDL(Hardware Design Language) netlist that describes the FPGA architecture, utilizing the model to automatically generate the bitstream of routing resource on the routing path based on the routing result. Our experimental results using a homogeneous SRAM FPGA with 30 million gates that contains 30 million configuration bits have shown a 298 times improvement in time efficiency, from 6 days when manually extracting the configuration bitstream model to 29 minutes when using MCMS to complete the extraction. For a heterogeneous FPGA of the same scale, it takes one week for the manual method to extract the configuration bitstream model, while the MCMS only needs 26 minutes, which improves the time efficiency by 394 times. By using the automatic method, not only the time for generating configuration bitstream can be shortened, but also the correctness of configuration bitstream generated can be ensured. As a general configuration bitstream model extracting procedure, the proposed approach is applicable for homogeneous and heterogeneous FPGAs.