Study of selectively buried ion-exchange glass waveguides using backside masking

Chongyang Pei; Gencheng Wang; Bing Yang; Longzhi Yang; Yinlei Hao; Xiaoqing Jiang; Jianyi Yang

doi:doi:10.3788/COL201513.021301

Chinese Optics Letters, 2015, 13 (2): 021301, Published Online: Sep. 25, 2018

Study of selectively buried ion-exchange glass waveguides using backside masking Download： 1252次

Chongyang Pei ¹Gencheng Wang ¹Bing Yang ¹Longzhi Yang ¹Yinlei Hao ^1,2Xiaoqing Jiang ^1,2Jianyi Yang ^1,2,*

Author Affiliations

¹ Department of Information Science and Electronics Engineering, Zhejiang University, Hangzhou 310027, China

² Cyrus Tang Center for Sensor Materials and Applications, Zhejiang University, Hangzhou 310027, China

Figures & Tables

Fig. 1. Schematic of the chip, and the definition of D.

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Fig. 2. Process flow for the realization of SBWs. (a) The mask deposition, photolithography process, and chemical etching and backside mask deposition. (b) The thermal Ag+/Na+ exchange. (c) The chemical etching of both masks. (d) The backside dielectric mask deposition. (e) The electric-assisted ion-diffusion.

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Fig. 3. (a) Buried depth. (b) The output cross-section view of the waveguides.

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Fig. 4. The schematic of the different regions of the SBW.

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Fig. 5. The measured IL of the SBWs, with the different lengths of the backside mask.

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Chongyang Pei, Gencheng Wang, Bing Yang, Longzhi Yang, Yinlei Hao, Xiaoqing Jiang, Jianyi Yang. Study of selectively buried ion-exchange glass waveguides using backside masking[J]. Chinese Optics Letters, 2015, 13(2): 021301.

Study of selectively buried ion-exchange glass waveguides using backside masking Download： 1252次

Fig. 1. Schematic of the chip, and the definition of D.

Fig. 3. (a) Buried depth. (b) The output cross-section view of the waveguides.

Fig. 4. The schematic of the different regions of the SBW.

Fig. 5. The measured IL of the SBWs, with the different lengths of the backside mask.

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Study of selectively buried ion-exchange glass waveguides using backside masking Download： 1252次

Fig. 1. Schematic of the chip, and the definition of D.

Fig. 3. (a) Buried depth. (b) The output cross-section view of the waveguides.

Fig. 4. The schematic of the different regions of the SBW.

Fig. 5. The measured IL of the SBWs, with the different lengths of the backside mask.

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