Digital-analog hybrid optical phase-lock loop for optical quadrature phase-shift keying

Shaowen Lu; Yu Zhou; Funan Zhu; Jianfeng Sun; Yan Yang; Ren Zhu; Shengnan Hu; Xiaoxi Zhang; Xiaolei Zhu; Xia Hou; Weibiao Chen

doi:doi:10.3788/COL202018.090602

Chinese Optics Letters, 2020, 18 (9): 090602, Published Online: Jul. 31, 2020

Digital-analog hybrid optical phase-lock loop for optical quadrature phase-shift keying Download： 933次

Shaowen Lu ^1,2,3,*Yu Zhou ¹Funan Zhu ^2,3Jianfeng Sun ^1,2Yan Yang ³Ren Zhu ³Shengnan Hu ³Xiaoxi Zhang ³Xiaolei Zhu ^1,2Xia Hou ^2,3,**Weibiao Chen ^1,2

Author Affiliations

¹ Key Laboratory of Space Laser Communication and Detection Technology, Shanghai Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Shanghai 201800, China

² Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

³ Laboratory of Space Laser Engineering, Shanghai Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Shanghai 201800, China

Figures & Tables

Fig. 6. (a) Frequency fluctuation PSD of the transmitter (TX)/receiver (RX) laser and (b) the constellation of the QPSK modulation signal.

下载图片查看原文

Fig. 7. QPSK fourth-power phase-lock loop simulation: (a) the Lissajous of the original signal sampled by 125 MSa/s; (b) the fourth power of the original signal; (c) phase error of the phase-locked state; (d) the constellation of the recovered IQ signal.

下载图片查看原文

Fig. 8. BER versus received signal power for 2.5 Gbaud/5 Gbaud.

下载图片查看原文

Table1. Experimental Parameters

Parameter	Symbol	Value
Laser wavelength	$λ$	1549.72 nm
Received signal power	$P_{s}$	−45 to $- 35 dBm$
Communication rate	$R_{b}$	10 Gbps
Linewidth (TX/RX)	$Δ ν$	300 Hz
Responsivity	$R$	0.85 A/W
Power-splitting ratio	$K$	0.5

查看原文

Table2. Specification List about FPGA

Name	Parameter
Fourth-power look-up table	Input bitwidth: 7 bitOutput bitwidth: 10 bit
First-order active loop filter	Input bitwidth: 10 bitOutput bitwidth: 32 bit
Direct digital synthesizer	Phase accumulator word: 32Output bitwidth: 16 bit
Working clock	125 MHz

查看原文

Shaowen Lu, Yu Zhou, Funan Zhu, Jianfeng Sun, Yan Yang, Ren Zhu, Shengnan Hu, Xiaoxi Zhang, Xiaolei Zhu, Xia Hou, Weibiao Chen. Digital-analog hybrid optical phase-lock loop for optical quadrature phase-shift keying[J]. Chinese Optics Letters, 2020, 18(9): 090602.

Digital-analog hybrid optical phase-lock loop for optical quadrature phase-shift keying Download： 933次

Fig. 1. Schematic of the QPSK fourth-power phase-lock loop.

Fig. 2. Principle of electro-optic modulation frequency shift as OVCO.

Fig. 3. Linear model of the analog fourth-power OPLL.

Fig. 4. Phase-error standard deviation versus loop natural frequency.

Fig. 5. Optimized natural frequency versus loop delay time.

Fig. 6. (a) Frequency fluctuation PSD of the transmitter (TX)/receiver (RX) laser and (b) the constellation of the QPSK modulation signal.

Fig. 7. QPSK fourth-power phase-lock loop simulation: (a) the Lissajous of the original signal sampled by 125 MSa/s; (b) the fourth power of the original signal; (c) phase error of the phase-locked state; (d) the constellation of the recovered IQ signal.

Fig. 8. BER versus received signal power for 2.5 Gbaud/5 Gbaud.

Table1. Experimental Parameters

Table2. Specification List about FPGA

关于本站 Cookie 的使用提示

全站搜索

Digital-analog hybrid optical phase-lock loop for optical quadrature phase-shift keying Download： 933次

Fig. 1. Schematic of the QPSK fourth-power phase-lock loop.

Fig. 2. Principle of electro-optic modulation frequency shift as OVCO.

Fig. 3. Linear model of the analog fourth-power OPLL.

Fig. 4. Phase-error standard deviation versus loop natural frequency.

Fig. 5. Optimized natural frequency versus loop delay time.

Fig. 6. (a) Frequency fluctuation PSD of the transmitter (TX)/receiver (RX) laser and (b) the constellation of the QPSK modulation signal.

Fig. 7. QPSK fourth-power phase-lock loop simulation: (a) the Lissajous of the original signal sampled by 125 MSa/s; (b) the fourth power of the original signal; (c) phase error of the phase-locked state; (d) the constellation of the recovered IQ signal.

Fig. 8. BER versus received signal power for 2.5 Gbaud/5 Gbaud.

Table1. Experimental Parameters

Table2. Specification List about FPGA

相关论文

相关资讯

关于本站 Cookie 的使用提示

全站搜索