1. INTRODUCTION

Driven by the urgent demand of applications in low cost, low power consumption and high-bandwidth interconnects, and the compatibility with complementary metal-oxide semiconductor (CMOS) processes, silicon photonics has been recognized as a promising technology to merge both optical and integrated circuits in a compact size and form new functional chips [1]. The intrinsic high-index-contrast in silicon waveguides results in compact size but also introduces strong polarization dependence. As a result, the silicon-based devices can only work well with either TE or TM polarization in general, and any decline in the purity of the operating polarization may cause serious performance degradation [2]. One common solution to tackle this problem is to deploy the polarization diversity scheme, in which polarization handling devices like polarization beam splitters (PBSs) [35" target="_self" style="display: inline;">–5] and rotators [68" target="_self" style="display: inline;">–8] are essential building blocks. In contrast with the increased complexity and system footprint that PBSs and rotators may bring, the on-chip polarizers offer another simple and effective approach to retain only one polarization in the system. On top of that, they also play vital roles in the applications of optical sensing [9] and communications [10].

Conventional on-chip polarizers [11–15" target="_self" style="display: inline;">–15], which are realized by dielectric schemes, normally result in a long device. For example, earlier work like Ref. [11] used a shallowly etched ridge waveguide to form a TE-pass polarizer with a device length of 1 mm, and the consequent large footprint was not suitable for highly dense integration. For this reason, several types of silicon-based polarizers [16–20" target="_self" style="display: inline;">–20] have been proposed lately to shorten the device, but they have their own drawbacks. Polarizers based on photonic crystals [16,17] suffer from large insertion loss for the selected polarization and challenging fabrication process, while a subwavelength grating-based polarizer [18], which acts as a polarization-dependent Bragg reflector, is plagued by its large back-reflection. Although polarizers utilizing symmetric shallowly etched waveguides [19] and narrow waveguide section [20] appear to achieve both compact size (2.5 μm in Ref. [19] and 18 μm in Ref. [20]) and good performance, they are not based on the commonly used silicon-on-insulator (SOI) platform, where the typical Si layer thickness is 220 or 340 nm. Moreover, a unique idea using polarization-dependent resonant tunneling [21] has shown potential to achieve ultrashort device length (1.35 and 1.31 μm for TE-pass and TM-pass polarizers, respectively), but the additional silicon layer in the buried oxide layer is not realistic to be deposited by conventional SOI process.

As a promising approach to further increase the integration density of silicon photonic circuits, surface plasmon polaritons (SPPs) have shown great potential to realize ultracompact devices due to the unique properties of nanoscale optical field confinement [22]. Thus far, many hybrid plasmonic-based polarizers have been demonstrated [23–30" target="_self" style="display: inline;">–30], but the large insertion loss is a big issue in that it may increase the output power requirement of the laser and the cost of thermal management on chip. The ordinary mechanism, e.g., introducing polarization-dependent loss [24–27" target="_self" style="display: inline;">–27], tends to make the device’s cross-section have a large interaction area between the metal layer and optical field, which is the primary cause of the considerable loss. Alternatively, by adjusting cut-off conditions to shorten the interaction length (0.8 μm) [30], the insertion loss (0.88 dB) can be reduced but is still relatively large, let alone the difficult fabrication. Other mechanisms that are later applied, such as directional coupling [28] and Bragg effect [29], have been proven as effective approaches to achieve ultralow loss (<0.1dB), but both of them have significant defects. As for the former, the long device length (30 μm) makes it lose the advantage of using SPPs; for the latter, the large reflection (−2.5dB) is intolerable from a practical perspective. Despite these attempts to solve the big issue of large insertion loss, other appropriate methods need to be explored to achieve a real breakthrough.

In this paper, we present a low-loss hybrid plasmonic TM-pass polarizer based on polarization-dependent mode conversion. Taking advantage of the hybrid plasmonic slot waveguide (HPSW) as the core conversion component, strong structural asymmetry can be introduced with a small interaction area between the metal and optical field, so efficient TE0‐to‐TM1 conversion can be obtained in a compact region while not affecting the pass of TM fundamental mode. Any first higher-order mode produced in the conversion process will be further suppressed by the compact slot-to-strip mode convertor, which acts as a role of “power combiner,” to avoid obvious reflection, and its energy will be scattered into the cladding. Unlike those possessing obvious defects or compromising the device size, this method can result in good comprehensive performance. The polarizer has a moderate footprint of 2.38μm×10μm with a short active length of only 5.5 μm. At the central wavelength of 1550 nm, the insertion loss (IL) can be kept around 0.4 dB, while the extinction ratio (ER) is as high as 28.3 dB. In addition, the average reflection of TE mode is suppressed below −14dB, and the bandwidth is approximately 65 nm when the extinction ratio is above 15 dB. This paper extends the idea of designing on-chip polarizers and paves the way toward practical use of hybrid plasmonic devices.

2. STRUCTURE AND WORKING PRINCIPLE

Figure 1(a) shows a schematic diagram of the proposed hybrid plasmonic TM-pass polarizer, which is based on the 340 nm SOI platform with SiO2 upper cladding. The main body of the active region [inset (ii) in Fig. 1(a)] is constructed by the HPSW and is connected to the input and output single-mode strip waveguide with two strip-slot mode convertors [inset (i) in Fig. 1(a)]. As Fig. 1(b) depicts, the active region possesses a polarization-dependent mode-conversion process, which constitutes the design principle of the proposed device. When the TE fundamental mode (TE0slot) is launched into the active region, most of the output power will convert to TM first-order mode (TM1slot) with a little remaining in the TE0slot; for TM fundamental mode (TM0slot) incidence, it can pass through the whole region with small propagation loss and only little optical power will convert to TE first-order mode (TE1slot). After that, the output slot-to-strip mode convertor functions as a “power combiner” to strip off any first higher-order modes. Thus, to function as a low-loss and high-ER TM-pass polarizer, the active region should feature both maximized TE0slot−to−TM1slot conversion and minimized TM0slot−to−TE1slot conversion. In addition, the strip-to-slot mode convertor should also ensure efficient coupling between the strip and slot waveguides for TM mode incidence. To further explain the above-mentioned polarization-dependent conversion process and fully understand the working principle of the device, both the active region and the strip-to-slot mode convertor are investigated in the following.

Fig. 1. (a) Schematic of the proposed TM-pass polarizer. Inset: (i) Compact strip-to-slot mode convertor; (ii) HPSW active region; (iii) cross-section of the HPSW. As an example, the widths of “rails” (Wsi) and slot (Wslot) in the HPSW are chosen as 240 and 180 nm, while the width of metal layer (Wm) is chosen as 300 nm. Besides, the inner radius (R1) and outer radius (R2) of the metal “wing” in ARS are set as 500 and 800 nm in our design, respectively. Under this structural configuration, the dielectric slot waveguide supports four eigenmodes: TE0slot, TE1slot, TM0slot, and TM1slot. (b) The polarization-dependent mode-conversion process in the proposed device.

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As shown in Fig. 1(b), the active region is composed of multimode interference (MMI) section and antireflection section (ARS). The former plays a central role in the mode-conversion process, while the latter is used to avoid the undesired reflection. The “MMI section” is formed by the HPSW, which can be regarded as a combination of dielectric slot and metal strip waveguides. Since they are close to each other, their field distribution will be coupled to form new eigenmodes. As illustrated in Figs. 2 and 3, there are six guided eigenmodes (EM1–EM6). The effect of the metal on the eigenmodes is not only reflected in the increasing number but also in the rotation of the optical axes. At the termination of the MMI section, the ARS constructed by a couple of metal “wings” is connected to avert the abrupt change of refractive index profile along the propagation direction (z axis). Moreover, the tips of the metal “wings” can efficiently prevent the optical power that coupled into the s-polarization mode in the metal strip from travelling back around its outer edge, which is another source causing undesired reflection. If we ignore the radiation modes, the incident TE0slot or TM0slot can be decoupled and rebuilt by the six guided eigenmodes in the MMI section. Although the plasmonic waveguide is a non-Hermitian system due to the losses of eigenmodes resulting from the metal layer, the six hybrid plasmonic eigenmodes still constitute a complete quasi-orthogonal space. Therefore, the optical field {ϕEc, ϕHc} propagating in the MMI section can be expressed by where {ϕED, ϕHD} and {ϕEi, ϕHi} represent the normalized transverse electromagnetic field of the input dielectric mode (TE0slot or TM0slot) and the hybrid plasmonic eigenmodes (EMi) propagating in the HPSW along the +z direction with the complex propagation constant βi=neffik0. The coupling coefficient for EMi (i=1–6) at the input facet of the HPSW (z=0) can be calculated based on Eq. (3) and only hybrid plasmonic eigenmodes possessing identical modal symmetry with the incident dielectric mode can be excited. These calculations are conducted by extracting the mode profile data from Lumerical FDTD and conducting further numerical analysis in MATLAB. Therefore, for TE0slot incidence, only EM2, EM4, and EM5 will be stimulated, and their power coupling ratios (γi=|ai|2) are depicted in Figs. 2(d)–2(f). These results indicate that more than 95% of the input power is coupled to these three eigenmodes, while EM2 and EM4 account for the majority (>78%). Because these three stimulated eigenmodes have a tilted electric field [black arrows shown in Figs. 2(a)–2(c)], they will beat with each other and accumulate phase shift while travelling through the HPSW. Similar to the self-imaging principles [31], the incident optical power, TE0slot mode, will be reconstructed into TM1-like mode periodically along the propagation direction. If the MMI section is terminated at a nonspecific length, the output power will couple to TM1slot and TE0slot, which can be verified by mode similarity. For TM0slot incidence, as shown in Figs. 3(d)–3(f), most of the input power is coupled to the EM1 due to its large mode similarity with TM0slot, while a little is coupled to the EM3. In a similar way, the output power will be coupled to TM0slot and TE1slot. The proportion of γ1 will rise to more than 90% when the metal layer moves as far as possible away from the silicon sidewall. Unlike eigenmodes having a tilted electric field, however, the optical axis of EM1 and EM3 remains almost the same as that of TM0slot and TE1slot. Hence, no mode beating will occur during their propagation in the HPSW.

Fig. 2. Transverse magnetic-field profile of (a) EM2, (b) EM4, and (c) EM5. Black arrows represent the electrical field directions. Corresponding power coupling ratios of (d) EM2, (e) EM4, and (f) EM5 with sweeping Gap and Hm when TE0slot is injected into the HPSW. The mode profiles for TE0slot, EM2, EM4, and EM5 are given under the dimension that Wsi=240nm, Wslot=180nm, Wm=300nm, Gap=45nm, and hAu=45nm.

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Fig. 3. Transverse magnetic-field profile of (a) EM1, (b) EM3, and (c) EM6. Black arrows represent the electrical field directions. Corresponding power coupling ratios of (d) EM1, (e) EM3, and (f) EM6 with sweeping Gap and Hm when TM0slot is injected into the HPSW. The mode profiles for TM0slot, EM1, EM3, and EM6 are given under the dimension that Wsi=240nm, Wslot=180nm, Wm=300nm, Gap=45nm, and hAu=45nm.

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On one hand, to maximize the TE0slot‐to‐TM1slot conversion efficiency, termination of the MMI section should be selected at half beat length (Lm), where the first destructive interference pattern of Ex appears. This length can be determined by calculating the mode-overlap ratio (Γ) between the TM1-like mode on the termination facet and TE0slot in the output dielectric slot waveguide. This variable is used to evaluate the completeness of the TE0slot‐to‐TM1slot conversion. The smaller the value, the more complete the conversion from TE0slot to TM1slot: For each swept parameter pair (Gap, Hm), only minimized Γ and its corresponding Lm will be recorded, and a 2D parameter space for these two figure of merits is plotted in Figs. 4(a) and 4(b). The smallest Γ is achieved when (Gap, Hm) is chosen as (35, 50) nm. Apart from this lowest point, other three extreme points [green stars shown in Figs. 4(a)], which are located at (30, 45) nm, (45, 45) nm, and (60, 30) nm, also have great potential to achieve efficient TE0slot‐to‐TM1slot conversion. On the other hand, the low-loss transmission of TM0slot should also be realized simultaneously, and the conversion from TM0slot to TE1slot ought to be minimized. Thus, only (Gap, Hm) = (60, 30) nm is the most suitable choice, since Fig. 3(d) shows that both γ1>94% and γ3<3% can be achieved if the Gap is kept no less than 60 nm with Hm lower than 40 nm. Under this pair of parameter settings, the half beat length is Lm=5.44μm. However, this is not the final length of the MMI section in the real polarizer since the effective conversion length (Leff) contributed from ARS has not yet been considered. So, to further determine the actual length of the MMI section (Ls), we employ the 3D finite-element-time-domain (FDTD) simulation to analyze the whole active region for TE0slot incidence by sweeping this structural parameter (Ls) and extract the mode-overlap ratio [red-dotted line in Fig. 4(c)]on the output facet of the dielectric slot waveguide. The comparison between the mode overlap ratios with and without ARS [Fig. 4(c)] shows that the sharp bend of ARS (R1=500nm) will provide an effective conversion length of 440 nm; thus, the actual length of the MMI section is only 5 μm. What is more, the shallower depth of the valley floor (red-dotted line) indicates that the existence of ARS will decrease the purity of the TM1slot in the output power, since the gradually increasing gap between silicon sidewall and sharp bend in the ARS will lead to the incomplete elimination of the Ex component.

Fig. 4. (a) Mode overlap ratio after taking logarithm between the mode field on the termination facet of MMI section and TE0slot in the output dielectric slot waveguide. (b) Corresponding Lm with Gap and Hm varied. (c) Comparison between the mode overlap ratio with and without ARS.

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3. LOW-LOSS HYBRID PLASMONIC TM-PASS POLARIZER

In the above section, the polarization-dependent mode-conversion process in the active region has been analyzed, and the optimized structure to realize both maximum TE0slot‐to‐TM1slot conversion and minimum TM0slot‐to‐TE1slot conversion has also been found. In order to minimize the insertion loss and the length of the whole polarizer, a low-loss and compact strip-to-slot mode convertor is also needed. Herein, we present a structure, as illustrated in Fig. 5. The width of the silicon waveguide W is increased sinusoidally along the propagation direction, so that the incident mode can be expanded smoothly and pass through the mode convertor in an adiabatic way. To simplify the analysis, we choose Lc=1.5μm and L2=0.2μm as an example to employ the following optimization for TM fundamental incidence. The insertion loss for a single strip-to-slot mode convertor (ILc) is evaluated by the equation in the inset of Fig. 5, and a lowest value of approximately 0.1 dB can be achieved when Wt is selected as 0.89 μm.

Fig. 5. Insertion loss of the strip-to-slot mode convertor (ILc) varied with respect to Wt (for TM0 incidence). Inset: The transverse magnetic field evolution in the proposed strip-to-slot mode convertor and its schematic diagram of structural parameters.

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To fully illustrate the concept, the entire polarizer is studied by employing the 3D FDTD method. To stabilize the converted mode, a certain length of dielectric slot waveguide is reserved before and after the active region, so that the final total length of the polarizer is 10 μm. The electric-field evolutions in the polarizer for both TE and TM fundamental mode incidence are demonstrated in Fig. 6. In particular, three key performance parameters are evaluated, including the extinction ratio ER [ER=10log10(ToutTM/ToutTE)], insertion loss IL [IL=|10log10(ToutTM)|=|ILactive+2ILc|], and reflection. ToutX stands for the transmissivity of X-polarization (X=TE or TM) after passing through the entire polarizer. The wavelength dependence of the transmissivity for both polarization incidences is investigated in Fig. 7(a). The transmissivity for TM remains almost invariable across the entire wavelength range, while that for TE hits the bottom, which is about −28.7dB, at the central wavelength of 1550 nm. Moreover, ER reaches the peak of 28.3 dB at the wavelength of 1550 nm, and the bandwidth of ER>15dB is about 65 nm. The average reflection for TE and TM fundamental incidence can be controlled below −14dB and −22dB, respectively, for the entire C band. The fluctuation of reflection comes from the fact that a small amount of reflection will be generated in the output slot-to-strip mode convertor from the diffraction process and then will result in the consequent resonance in the active region. The insertion loss for the whole device can be kept below 0.45 dB for the entire C band, while the loss induced by the active region is only 0.2 dB at 1550 nm. Finally, the fabrication tolerance of the ER and IL is shown in Figs. 7(e) and 7(f), which assumes that the central positions of both silicon and metal strips are accurate, while their widths W_si and Wm are changed by ΔW. The IL is not sensitive to the fabrication imperfection, while ER changes remarkably because the dimension deviations (ΔWsi and ΔWm) have negligible influence on the mode similarity between TM0slot and EM1 but change the optimal destructive interference condition for TE fundamental incidence. If ER>15dB is required, ΔWm and ΔWsi should be controlled within the range of (−16, 20) nm and (−30, 10) nm, respectively.

Fig. 6. Electric-field evolution with the corresponding (b), (e) Ex and (c), (f) Hx component in the proposed TM-pass polarizer for (a) TE and (d) TM fundamental input. The operation wavelength is 1550 nm, and the refractive indices for gold, SiO2, and Si are 0.238+11.263i [32], 1.444, and 3.478, respectively. Besides, the minimum mesh of 5 nm in x, y, and z directions is set to obtain accurate and stable results.

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Fig. 7. Wavelength dependence of (a) transmissivity, (b) ER, (c) reflection, and (d) IL of the proposed device. ER and IL versus (e) ΔWm and (f) ΔWsi.

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4. CONCLUSION

In summary, we have demonstrated a low-loss hybrid plasmonic TM-pass polarizer based on HPSW structure. By using polarization-dependent mode conversion to convert and eliminate the unwanted polarization, the metal layer in the HPSW can provide strong structural asymmetry while maintaining small thickness of the metal layer that reduces its interaction area with the optical field. This trait of the idea guarantees that high extinction ratio (28.3 dB) and low loss (0.4 dB) can be realized simultaneously; further, it has also pushed the balance between footprint and performance of the plasmonic devices to a more realistic and competitive point. The same approach by using polarization-dependent mode conversion to design high-performance on-chip polarizers can be applied on other integration platforms.