基于FPGA的高速QKD系统保密增强算法实现

路后兵; 赵军; 阴泽杰

doi:doi:10.3969/j.issn.1007-5461. 2019.02.011

量子电子学报, 2019, 36 (2): 197, 网络出版: 2019-04-03

基于FPGA的高速QKD系统保密增强算法实现

Implementation of FPGA based privacy amplification for high speed QKD system

论文大纲

路后兵 ^1,*赵军 ¹阴泽杰 ²

作者单位

¹ 中国人民解放军国防科技大学电子对抗学院, 安徽合肥 230037

² 中国科学技术大学近代物理系, 安徽合肥 230026

摘要

量子密钥分发(QKD)过程中,保密增强算法用于消除QKD过程本身泄露以及可能被窃听者窃取的密钥信息,从而保证生成的量子密钥的安全。现有多种CPU软件实现方案。为提高算法安全性、集成度,并降低功耗,研究了采用FPGA实现的高速Toeplitz矩阵相乘保密增强算法方案。通过采用矩阵分块并行计算、流水线结构等加速运算方法,该方案在每次处理256 Kbits输入密钥时最大安全成码速率达到20 Mbps,在每次处理1 Mbits输入密钥时最大安全成码速率达到5 Mbps。此外,还能适应一次计算1 Mbits内任意长度的输入密钥,也能适应0～1之间的任意压缩比例,有助于未来实用化高速QKD系统研制。

Abstract

In the process of quantum key distribution (QKD), privacy amplification can eliminate the leaked information of the key data in the QKD process itself and the key information that may be intercept by the eavesdropper, thus ensure the security of the generated quantum key. There are several schemes to realize privacy amplification algorithm based on CPU software. In order to improve the implementation security of this algorithm and the integration level, reduce the power consumption, the implementation of high speed Toeplitz matrix multiplication privacy amplification algorithm based on FPGA was researched. By using matrix block parallel computation, pipeline structure and other accelerated operation methods, the maximum bandwidth of secure key rate of this scheme is up to 20 Mbps when processing 256 kbits input key each time, and up to 5 Mbps when processing 1 Mbits input key each time。In addition, this scheme can adapt to input key length within 1 Mbits, and also adapt to the compress ratio between 0～1, which is conducive to the development of practical high-speed QKD system in the future.

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路后兵, 赵军, 阴泽杰. 基于FPGA的高速QKD系统保密增强算法实现[J]. 量子电子学报, 2019, 36(2): 197. LU Houbing, ZHAO Jun, YIN ZeJie. Implementation of FPGA based privacy amplification for high speed QKD system[J]. Chinese Journal of Quantum Electronics, 2019, 36(2): 197.

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