采用65 nm CMOS工艺,基于时间域4倍插值技术,设计了一款6位3.4 GS/s Flash ADC。该插值技术可以将N位Flash ADC的比较器数量从传统的2N-1减少到2N-2。与传统插值技术不同,该技术利用简单的SR锁存器有效地实现了4倍插值因子,而无需额外的时钟和校准硬件开销,在插值阶段只需要校准2N-2个比较器的失调电压。在不同的工艺角、电源电压和温度(PVT)下,SR锁存器中的失调电压不超过±0.5 LSB。该ADC的采样频率达到3.4 GS/s,其在Nyquist输入时的ENOB达到5.4位,在1 V电源下消耗12.6 mW的功耗,其Walden FoM值为89 fJ/(conv·step)。

Sensitivity and data processing speed are important in spectral domain Optical Coherence Tomography (SD-OCT) system. To get a higher sensitivity, zero-padding interpolation together with linear interpolation is commonly used to re-sample the interference data in SD-OCT, which limits the data processing speed. Recently, a time-domain interpolation for SD-OCT was proposed. By eliminating the huge Fast Fourier Transform Algorithm (FFT) operations, the operation number of the time-domain interpolation is much less than that of the zero-padding interpolation. In this paper, a numerical simulation is performed to evaluate the computational complexity and the interpolation accuracy. More than six times acceleration is obtained. At the same time, the normalized mean square error (NMSE) results show that the time-domain interpolation method with cut-off length L = 21 and L = 31 can improve about 1.7 dB and 2.1 dB when the distance mismatch is 2.4mm than that of zero-padding interpolation method with padding times M = 4, respectively. Furthermore, this method can be applied the parallel arithmetic processing because only the data in the cut-off window is processed. By using Graphics Processing Unit (GPU) with compute unified device architecture (CUDA) program model, a frame (400 A-lines × 2048 pixels × 12 bits) data can be processed in 6 ms and the processing capability can be achieved 164,000 line/s for 1024-OCT and 71,000 line/s for 2048-OCT when the cut-off length is 21. Thus, a high-sensitivity and ultra-high data processing SD-OCT is realized.