Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications. Being still in an early development phase, vertical GaN devices are yet to be fully optimized and require careful studies to foster their development. In this work, we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs (TMOS’s) provided by TCAD simulations, enhancing the dependability of the adopted process optimization approaches. Specifically, two different TMOS devices are compared in terms of transfer-curve hysteresis (H) and subthreshold slope (SS), showing a ≈ 75% H reduction along with a ≈ 30% SS decrease. Simulations allow attributing the achieved improvements to a decrease in the border and interface traps, respectively. A sensitivity analysis is also carried out, allowing to quantify the additional trap density reduction required to minimize both figures of merit.

为了满足脉冲电场消融的应用需求，解决单极性脉冲电场分布不均匀的问题，研制了一台基于半桥结构的主电路、具有纳秒级前沿的高重复频率双极性亚微秒高压脉冲电源。该脉冲电源由FPGA提供控制信号，经过驱动芯片放大控制信号后，利用光耦隔离驱动多个SiC MOSFET。驱动电路所需元器件较少，信号控制时序简单，可提供负压偏置，使开关管可靠关断，提高了电路的抗电磁干扰能力，使电源能稳定运行。通过电阻负载实验，对比分析了不同栅极电阻对驱动电压的影响，驱动电压上升沿时间越短对应的双极性高压脉冲前沿越快。实验结果表明：所设计的高频双极性脉冲电源在100 Ω纯阻性负载上能够稳定产生重复频率双极性纳秒脉冲，输出电压0～±4 kV可调，脉宽0.2～1.0 μs可调，正负脉冲相间延时0～1 ms可调，上升沿和下降沿60～150 ns之间。该双极性脉冲电源电路设计结构紧凑，能满足应用的参数需求。

作为脉冲系统的核心部件，开关承担着脉冲成形、功率调制等重要作用，开关通断速度往往决定脉冲上升时间，高速开关是纳秒短脉冲形成的关键。提出一种高速SiC-MOSFET叠层封装结构，整体布局无引线、无外接，具有极低寄生电感。开展了电磁场仿真研究，揭示了脉冲形成过程中封装多介质界面电磁场分布规律，明确了封装结构电磁薄弱环节，为进一步绝缘优化提供指导。搭建双脉冲测试平台，对研制的SiC-MOSFET叠层封装开关与同芯片商用TO-263-7封装开关的动态性能进行测试。结果表明，大电流工况下，所提封装电流开通速度提升48%，关断速度提升50%，开通损耗降低54.6%，关断损耗降低62.8%，实验结果验证了所提叠层封装结构对开关动态性能的改善。

为实现全固态Marx发生器中多个SiC MOSFET开关的同步驱动，设计了一种基于脉冲变压器的驱动控制电路。多路驱动信号的同步性会影响到Marx发生器的输出波形参数，因此要求驱动信号具有快脉冲前沿、低抖动特点。根据SiC MOSFET驱动原理及要求，分析了SiC MOSFET驱动电路脉冲前沿的影响因素，分析计算其相关参数，进行仿真模拟验证。设计了共初级穿芯10级串联的脉冲变压器，初次级的匝数分别为1匝和9匝，次级经正负脉冲信号调理电路后驱动10级Marx电路。实测结果表明利用脉冲变压器原边漏感与谐振电容构成的谐振电路在断续模式下，驱动功率越大，脉冲前沿越快且同步性越好。该同步驱动电路的脉冲前沿为112 ns，脉宽1～10 μs可调，频率10～25 kHz可调，满足固态Marx发生器参数调整需求。

The self-heating effect severely limits device performance and reliability. Although some studies have revealed the heat distribution of β-Ga₂O₃ MOSFETs under biases, those devices all have small areas and have difficulty reflecting practical conditions. This work demonstrated a multi-finger β-Ga₂O₃ MOSFET with a maximum drain current of 0.5 A. Electrical characteristics were measured, and the heat dissipation of the device was investigated through infrared images. The relationship between device temperature and time/bias is analyzed.

A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode (Hk-SJ-SBD MOSFET) is proposed, and has been compared with the SiC high-k MOSFET (Hk MOSFET), SiC superjuction MOSFET (SJ MOSFET) and the conventional SiC MOSFET in this article. In the proposed SiC Hk-SJ-SBD MOSFET, under the combined action of the p-type region and the Hk dielectric layer in the drift region, the concentration of the N-drift region and the current spreading layer can be increased to achieve an ultra-low specific on-resistance (R_on,sp). The integrated Schottky barrier diode (SBD) also greatly improves the reverse recovery performance of the device. TCAD simulation results indicate that theR_on,sp of the proposed SiC Hk-SJ-SBD MOSFET is 0.67 mΩ·cm² with a 2240 V breakdown voltage (BV), which is more than 72.4%, 23%, 5.6% lower than that of the conventional SiC MOSFET, Hk SiC MOSFET and SJ SiC MOSFET with the 1950, 2220, and 2220 V BV, respectively. The reverse recovery time and reverse recovery charge of the proposed MOSFET is 16 ns and18 nC, which are greatly reduced by more than 74% and 94% in comparison with those of all the conventional SiC MOSFET, Hk SiC MOSFET and SJ SiC MOSFET, due to the integrated SBD in the proposed MOSFET. And the trade-off relationship between theR_on,sp and the BV is also significantly improved compared with that of the conventional MOSFET, Hk MOSFET and SJ MOSFET as well as the MOSFETs in other previous literature, respectively. In addition, compared with conventional SJ SiC MOSFET, the proposed SiC MOSFET has better immunity to charge imbalance, which may bring great application prospects.