Underwater wireless optical communication (UWOC) has advantages such as high bandwidth, high data rate, low latency, and small form factor. It can support the transmission of high-speed, high-capacity, real-time, and multimedia services like underwater images and videos. Light-emitting diodes (LEDs) are cost-effective light sources with high energy efficiency, and their wide-angle beam profile relaxes the alignment requirements between the transmitter and receiver. However, high-power LED sources have narrow bandwidth and exhibit strong non-linear effects. Additionally, the underwater optical channel is affected by absorption, scattering, turbulence, and bubbles, while the photodetectors may also exhibit non-linear effects. These factors lead to non-linear distortion of the optical signal, severely affecting communication bandwidth and limiting transmission distance. The Volterra algorithm is commonly used for non-linear compensation in communication systems, but it has high complexity and computational overhead. Most existing research on the Volterra algorithm involves offline processing, which is not conducive to miniaturization and low power consumption in underwater environments. Therefore, we propose a low-complexity, low-power, and hardware-friendly 3l-sVolterra (link and linear list-based sparse Volterra) algorithm for UWOC systems. By combining new data structures based on linked lists and linear lists to store all the parameters of the Volterra algorithm, the on-chip resources required for updating the Volterra algorithm's parameters are effectively reduced. It also facilitates sparse processing of the participating non-linear terms, making it suitable for small-scale hardware systems. Compared with the 3l-Volterra algorithm without sparsity operations, this algorithm reduces resource consumption by 30% while preserving similar non-linear compensation capabilities. We hope that the proposed 3l-sVolterra algorithm can promote miniaturization and real-time underwater applications of UWOC systems.

The 3l-sVolterra algorithm utilizes a combined data format of linked lists and linear lists to store the parameters for Volterra operations. The algorithm achieves parameter updates through N multiplications, one node insertion, and traversal of the remaining N-1 nodes in the linked list, significantly improving the efficiency of each update and operation. The algorithm's sparse operations on the non-linear terms further reduce on-chip resource consumption. We implement and validate the 3l-sVolterra algorithm on a low-power and miniaturize digital signal processing (DSP) chip, the C6748. We also design a DSP subsystem based on the C6748 as the core. In the receiving end, the optical signal is converted into an electrical signal by an avalanche photo diode (APD). The electrical signal is then amplified and input to an analog-to-digital conversion (ADC) module. Finally, the converted digital signal is synchronized, demodulated, and subjected to non-linear equalization by the DSP subsystem.

In a 5 m-long underwater channel, the UWOC system employs the CAP-4 modulation scheme for data transmission. The experiment tests the compensation capability of the 3l-sVolterra algorithm in the entire UWOC system with four different memory lengths (10, 14, 18, and 20) and varying numbers of retained terms (4, 8, 12, and 16). As the memory length increases, the 3l-Volterra algorithm (the 3l-sVolterra algorithm without sparse operations) enhances the compensation capability of the entire UWOC system, achieving a channel bandwidth expansion of up to 20 Mbit/s. While maintaining similar non-linear compensation capabilities to the algorithm without sparsity operations, the 3l-sVolterra algorithm reduces on-chip resource consumption by 30%. When a non-linear compensation algorithm with a memory length of N is processed, the number of retained non-linear terms should be greater than N/2, so as to ensure the majority of non-linear compensation capability. The influence of non-linear terms beyond the N/2 range gradually diminishes. This algorithm is suitable for DSP hardware systems and can be ported to hardware systems of other architectures.

We propose a low-complexity, low-power, and hardware-friendly 3l-sVolterra algorithm. The algorithm adopts a new data structure that combines linked lists and linear lists to store all the parameters of the Volterra algorithm, effectively reducing the on-chip resources required for parameter updates. It also allows sparse operations on the non-linear terms of the Volterra algorithm and facilitates portability to different small-scale hardware systems. Furthermore, a DSP subsystem based on the 3l-sVol algorithm is implemented on the C6748 chip, and a UWOC system is constructed using a 5 m-long water tank to test the designed DSP subsystem. Compared with the 3l-Vol algorithm, the proposed algorithm reduces on-chip resource consumption by 30% while maintaining similar non-linear compensation capability. By changing the memory length and the number of retained terms in the Volterra algorithm, the variation of the algorithm's non-linear compensation capability in the constructed UWOC system is tested. Reducing the number of retained terms can effectively reduce the on-chip resource consumption of the Volterra algorithm. This is the first time that a non-linear equalization algorithm has been ported to a DSP chip, achieving synchronous data transmission and real-time non-linear compensation in the DSP-based UWOC system. The DSP subsystem has good compensation capability for both linear and non-linear distortions, as well as system bandwidth extension ability, which is of great significance for miniaturizing the UWOC system and promoting its real-time underwater applications.