采用65 nm CMOS工艺,基于时间域4倍插值技术,设计了一款6位3.4 GS/s Flash ADC。该插值技术可以将N位Flash ADC的比较器数量从传统的2N-1减少到2N-2。与传统插值技术不同,该技术利用简单的SR锁存器有效地实现了4倍插值因子,而无需额外的时钟和校准硬件开销,在插值阶段只需要校准2N-2个比较器的失调电压。在不同的工艺角、电源电压和温度(PVT)下,SR锁存器中的失调电压不超过±0.5 LSB。该ADC的采样频率达到3.4 GS/s,其在Nyquist输入时的ENOB达到5.4位,在1 V电源下消耗12.6 mW的功耗,其Walden FoM值为89 fJ/(conv·step)。

A 6-bit 3.4 GS/s flash ADC was designed in a 65 nm CMOS process based on the 4 fold time-domain interpolation technique which allowed the reduction of the number of comparators from the conventional 2N-1 to 2N-2 in a N-bit flash ADC. The proposed scheme achieved effectively a 4 fold interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage, where only offset between the 2N-2 comparators needed to be calibrated. The offset in SR-latches was within ±0.5 LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The prototype achieved 3.4 GS/s sampling frequency with 5.4 bit ENOB at Nyquist and consumed 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/(conv·step).