为保证智能电网中的数据安全,防止电力通信过程中的数据被篡改,安全芯片的应用必不可少,而RSA算法是安全芯片中应用最广泛的公钥算法之一。RSA算法复杂度高,硬件实现功耗较大,在设计的过程中常常无法完全兼顾性能、功耗、安全性等各个方面。文章设计了一种高性能、能抵抗常见侧信道攻击及EMA电磁攻击的高安全RSA协处理器。提出的随机存储模幂算法真伪运算结果的防护策略,增强了协处理器抵抗侧信道攻击、差分功耗攻击以及EMA电磁攻击的能力。通过两个层级的算法优化来提升协处理器性能,并通过结合CIOS平方算法和Karatsuba算法的改进的Montgomery模乘算法,使得1 024位带防护的RSA算法在UMC 55 nm工艺下的面积为4.8万门@30 MHz,功耗为4.62 mW@30 MHz,FPGA开发板上进行API测试的性能为709.3 kbit/s。

In order to prevent the data from being tampered in power communication in smart grid, security chip is essential, and RSA algorithm is one of the most widely used public key algorithms. However, due to the high complexity and power consumption of hardware implementation, it is unable to take the performance, power consumption, security into account. In this paper, a high secure and high performance RSA coprocessor was designed. The security strategy proposed enhanced the coprocessor's ability to resist side channel attack, differential power attack and EMA electromagnetic attack. Two levels of algorithm optimization were used to improve the coprocessor performance, and the improved Montgomery modular multiplication algorithm combined with CIOS square algorithm and Karatsuba algorithm made the 1 024 bit RSA algorithm with protection have an area of 48 000 gates @30 MHz and a power consumption of 4.62 mW @30 MHz under UMC 55 nm process. The performance of API test on FPGA board was 709.3 kbit/s.