基于350 nm 2-poly 3-metal EEPROM工艺，设计了一种应用于低频无源RFID的低成本2 kbit EEPROM存储器。在保证存储容量能满足大多数使用场景的情况下，通过优化Dickson电荷泵和读出电路的结构，实现电路版图面积的最小化，从而对整体电路实现低成本设计。优化后的Dickson电荷泵能实现10 μs内从3.3 V到16 V的稳定升压，且功耗为334 μW；读出电路基于检测NCG器件阈值电压的方式实现存储逻辑值的判别，该方法不需要能提供高精度电流的基准电路和具有高增益的灵敏放大器，有效降低了整体电路的面积。低成本2 kbit EEPROM的工作电压为3.3 V，能实现32位并行输入和1位串行输出，芯片总面积仅为0.14 mm2，有效降低了低频无源RFID设计复杂度和制造成本。

A low cost 2 kbit EEPROM memory was designed in a 350 nm 2-poly 3-metal EEPROM process for low frequency passive RFID applications. The design minimized the layout area by optimizing the Dickson charge pump and the readout circuit, while ensuring that the memory capacity could meet most usage scenarios. The optimized Dickson charge pump provided a stable voltage boost from 3.3 V to 16 V in 10 μs with the power consumption of 334 μW. The readout circuit was based on detecting the threshold voltage of the NCG device to discriminate the stored logic value, which eliminated the need for a high precision current reference circuit and a sensitive amplifier with high gain, effectively reducing the overall circuit area. The low cost 2 kbit EEPROM operated at 3.3 V and was capable of 32 bit parallel input and one-bit serial output, with a total chip area of 0.14 mm2, effectively reducing the complexity and manufacturing cost of low frequency passive RFID designs.