基于110 nm CMOS工艺设计了一种应用于HDMI接收端电路的宽频带低抖动锁相环。采用一种改进型双环结构电荷泵，在25～250 MHz的宽输入频率范围内实现了快速锁定。通过高相噪性能的伪差分环形振荡器产生了调谐范围为125 MHz～1.25 GHz的时钟信号。仿真实验结果表明，该锁相环的锁定时间小于1.2 μs，在振荡器工作频率为0.8 GHz时，其相位噪声为-100.0 dBc/Hz @1 MHz，输出时钟峰峰值抖动为4.49 ps。

A wide-band low jitter phase-locked loop applied to HDMI receiver circuit was designed in a 110 nm CMOS technology. The circuit used an improved charge pump with double loop structure to realize fast locking in a wide input frequency range of 25 ~ 250 MHz, and a clock signal with a tuning range of 125 MHz~ 1.25 GHz was generated through a pseudo differential ring oscillator with high phase noise performance. The simulation results show that the locking time of the PLL is less than 1.2 μs. When the operating frequency of the oscillator is 0.8 GHz, the phase noise is -100.0 dBc/Hz @ 1 MHz, and the peak to peak jitter of the output clock is 4.49 ps.