一种基于FPGA+DSP的处理机硬件架构

王占超; 张耀天

doi:doi:10.11805/tkyda201805.0902

太赫兹科学与电子信息学报, 2018, 16 (5): 902, 网络出版: 2019-06-10

一种基于FPGA+DSP的处理机硬件架构

Hardware architecture of processor based on FPGA+DSP structure

论文大纲

王占超 ^*张耀天

作者单位

北京航空航天大学电子信息工程学院，北京 100191

现场可编程门阵列+数字信号处理器多核数字信号处理器快速傅里叶变换效率 Field Programmable Gate Array(FPGA)+Digital Signal multi-core DSP Fast Fourier Transform(FFT) efficiency

摘要

为了解决在实时处理中多数合成孔径雷达(SAR)算法存在的运算量大、耗时长等问题，提出基于多核数字信号处理器(DSP)以及串行高速互联接口(SRIO)的一种新硬件解决方法。主要讨论了现场可编程门阵列(FPGA)+DSP架构下采用多核DSP和SRIO实现SAR算法的主要流程，并在多核DSP中使用流水线技术优化快速傅里叶变换(FFT)算法。通过使用多核DSP和流水线技术以及SRIO技术，使数据运算、传输速率更快，达到缩短运算时间的目的。

Abstract

A hardware architecture of processor based on Field Programmable Gate Array(FPGA)+ Digital Signal Processor(DSP) structure is proposed. In order to solve the problem of large amount of computation and long time in most real-time processing of Synthetic Aperture Radar(SAR) algorithm, a new hardware solution based on multi-core DSP and Serial Rapid I/O (SRIO) is proposed. Since multi-core DSP makes the processing speed in the chip faster and SRIO makes the data transmission between chips faster, this paper mainly discusses the main flow of implementing SAR algorithm by using multi-core DSP and SRIO based on FPGA+DSP architecture and optimizing the Fast Fourier Transform(FFT) algorithm by using pipeline technology in multi-core DSP. By using multi-core DSP, pipeline technology and SRIO technology, the data operation and transmission rate are faster, and the goal of shortening the calculation time is achieved.

参考文献

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王占超, 张耀天. 一种基于FPGA+DSP的处理机硬件架构[J]. 太赫兹科学与电子信息学报, 2018, 16(5): 902. WANG Zhanchao, ZHANG Yaotian. Hardware architecture of processor based on FPGA+DSP structure[J]. Journal of terahertz science and electronic information technology, 2018, 16(5): 902.

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