1 Introduction

Accurate extrinsic resistances extraction for modeling InP HEMT devices is a crucial step in the design and production of high-yield，low-cost millimeter wave circuits^［1］. The common used methods mainly include numerical optimization method，cold FET method and cutoff method. In optimization method，the extrinsic resistances extraction result strongly depends on the initial value and suffers from non-uniqueness and non-physical meaning^［2］. In cold FET method，the large gate currents caused by forward-biased run through the gate Schottky junction，which leads to degradation of the gate^［3-6］. To avoid degradation of device characteristics，some authors proposed cutoff method to extract extrinsic resistances. However，this method is valid only at high frequency（>18GHz），and the extracted resistances fluctuate widely over the whole frequency range of interest^［7-9］.

In order to overcome these limitations，an improved method for determination of extrinsic resistances is proposed. In contrast with previous publications，this extraction method offers the following advantages.

1）Under operating bias point（V_gs > V_th，V_ds = 0 V），the effect of channel between source and drain can be modeled by resistance R_ch，while the capacitance will be dominant under cutoff bias condition.

2）The semi-analytical method which is a combination of optimization method and analytical direct extraction method has been used to determine the extrinsic resistances.

3）This extraction method is verified with S-parameters on-wafer measurement up to 110 GHz.

Section Ⅱ gives the equivalent circuit model under operating bias point（V_gs > V_th，V_ds = 0 V）as well as the derivation of analytical expressions. Section Ⅲ gives the procedure of intrinsic parameters extraction. The measured and simulated results are presented in Section Ⅳ. The conclusion is given in Section Ⅴ.

1　Extrinsic resistances extraction

1.1　Equivalent circuit model

Fig.1 shows the small-signal equivalent circuit model under operating bias point（V_gs > V_th，V_ds = 0 V）. C_pgd，C_pg，and C_pd represent the extrinsic capacitances due to the pad connections. L_g，L_d，and L_s represent the extrinsic inductances of the gate，drain，and source feedlines. R_s and R_d represent the extrinsic resistances of the source and drain. R_g is the distributed gate resistance. C_gsa and C_gda represent intrinsic gain-source and gain-drain capacitances respectively. R_ch is the channel resistance when the channel between drain and source is open at zero drain bias and gate voltage above threshold voltage.

图 1. 偏置点（Vgs > Vth，Vds = 0 V）下的小信号等效电路模型

Fig. 1. The small-signal equivalent circuit model under operating bias point（V_gs > V_th，V_ds = 0 V）

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The intrinsic part of the equivalent circuit model，which exhibits a PI topology，so it is convenient to describe it by a Y matrix as：

Convert -parameters to -parameters：

The Z-parameters of intrinsic part with extrinsic resistances can be expressed as following：

Therefore，we have

By neglecting the high order term ，the extrinsic resistances can be obtained by analytical expressions from real part of -parameters：

where

C_gsa and C_gda can be determined at low frequencies：

1.2　Extrinsic parameters extraction

The pad capacitances can be determined by measuring an open test structure：

The extrinsic inductances L_g，L_d，and L_s can be determined from the imaginary part of Z-parameters（transformed from measured S-parameters）of the short test structure directly：

The extraction of extrinsic resistances can be based on the semi-analytical method which is a combination of optimization method and analytical direct extraction method. The extraction procedure is as follows.

1）De-embedding the pad capacitances and feedline inductances.

2）Set the initial value of the channel resistance R_ch .

3）Calculate the extrinsic resistances R_g，R_d，and R_s using（13）-（15）which can be expressed as functions of R_ch as well as frequency.

4）Set error criteria as follows：

Where represents the calculated S-parameters，and represents the measured S-parameters. represents the discrepancy between simulated and measured S-parameters. W_pq are the weighting factors.

5）If error criteria are small enough，the iterative process will be end.

图 2. 算法流程图

Fig. 2. Flow chart of the algorithm

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2　Intrinsic parameters extraction

The small-signal circuit model of intrinsic part of InP HEMT devices is illustrated in Fig. 3 after de-embedding the extrinsic parameters，and the intrinsic Y-parameters are described as^［3］：

图 3. 本征部分的小信号等效电路模型

Fig. 3. The small-signal circuit model of intrinsic part

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with

From the analytical expressions（27）-（30），the intrinsic element values can be obtained directly.

3　Results and discussion

In this paper，70 nm InP HEMT devices have been used with 2×30 μm gate width（number of gate fingers×unit gate width）. The S-paremeters on-wafer measurement up to 110 GHz using N5247 network analyzer with DC bias by an Agilent B1500A.

Fig. 4 shows the plot of extracted extrinsic resistances versus frequency using the presented semi-analytical method and cutoff method^［9］. As can be seen from Fig. 4，the extracted R_d and R_s using semi-analytical method are nearly constant versus frequency，while extracted R_d and R_s using cutoff method fluctuate widely versus frequency. These results verify that the proposed extraction method is better than cutoff method ^［10］.

图 4. 半分析方法和截止方法提取的寄生电阻数值对比

Fig. 4. Extracted extrinsic resistances using the proposed semi-analytical method and cutoff method

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Table 1 gives the values of extrinsic resistances extracted using semi-analytical method. The values of extrinsic capacitances and inductances are given in Table 2. The extracted intrinsic parameters in Section III are shown in Table 3.

The intrinsic elements listed in Table 2 are substituted into the equivalent circuit model for simulation. Fig. 5 shows the comparison between simulated and measured S-parameters under multi bias. Good agreement between simulated and measured S-parameters are observed in the frequency range of 1 GHz to 110 GHz，which verifies the validity of this developed method to determine the extrinsic resistances.

图 5. 1 GHz ~110 GHz 频率范围内多偏置下模拟和测量S参数对比曲线

Fig. 5. Comparison between simulated (lines) and measured (squares) S-parameters over the frequency range going：from 1 GHz to 110 GHz under multi bias

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Table 4 outlines a selection of the accuracy of S-parameters for four different bias points. As can been seen from this table，S₁₁ and S₂₁ maintain an accuracy of around 5%，S₁₂ has an accuracy of less than 5%，and S₂₂ has an accuracy of between 2%~5%.

4　Conclusion

An approach for determination of extrinsic resistances for 70 nm InP HEMT devices is proposed in this paper. Extrinsic resistances are described as functions of the intrinsic channel resistance，and optimum values can be obtained using semi-analytical method under operating bias point（V_gs > V_th，V_ds = 0 V）. Verification of this extraction method is presented by the good agreement between the simulated and measured S-parameters under multi bias over the frequency range up to 110 GHz.