针对传统三倍频器输出功率和匹配性能差的问题, 基于TSMC 0.18 μm CMOS工艺, 提出一种用滤波器作为匹配电路的三倍频器。该三倍频器输出匹配性能好、功率损耗小, 提高了三次谐波的输出功率。对晶体管静态特性进行分析, 进一步提升输出功率。流片后的实测结果表明, 在31.5~36 GHz输出频率范围内, 输入功率为0 dBm时, 最大输出功率为-6.2 dBm, 基波抑制比大于12.35 dBc, 二次谐波抑制比大于8.2 dBc。三倍频器的电源电压为1.8 V, 直流功耗为36.9 mW。核心电路面积为0.35 mm2。

To solve the problem of poor output power and matching performance of traditional frequency triplier, a triplier was proposed while a filter was used as matching circuit based on TSMC 0.18μm CMOS process. This triplier had good matching performance and low power loss, and the output power of the third harmonic was improved. The static characteristics of the transistor were analyzed to further improve the output power. The measured results after the flow showed that the maximum output power was -6.2 dBm when the input power was 0 dBm, the fundamental wave suppression ratio was greater than 12.35 dBc, and the second harmonic suppression ratio was greater than 8.2 dBc within range of 31.5~36 GHz output frequency. The DC power consumption was 36.9 mW at 1.8 V power supply. The core circuit area was 0.35 mm2.