一种面向存算的高速字线驱动电路

王雨桐; 虞致国; 车饶; 顾晓峰

doi:doi:10.13911/j.cnki.1004-3365.210241

微电子学, 2022, 52 (1): 47, 网络出版: 2022-06-14

一种面向存算的高速字线驱动电路

A High Speed Word Line Drive Circuit for Compute-in-Memory

论文大纲

王雨桐虞致国车饶顾晓峰

作者单位

江南大学电子工程系物联网技术应用教育部工程研究中心, 江苏无锡 214122

存算字线驱动电路高压高速 CIM word line drive circuit high voltage high speed

摘要

在非易失性存算芯片(CIM)中, 大规模阵列的栅极等效电容以及远距离传输导线的等效电容严重限制了字线驱动电路(WLDC)的切换速度。非易失性存算器件工作所需的多电压域的压差已远超字线驱动电路中单管耐压范围。文章提出了一种面向存算的高速字线驱动电路, 结合阵列的工作原理, 采取多级预处理电压控制方法, 将多电压域多种高压进行可选择的分级传输, 大幅降低了传播延时。采用箝位分压结构, 降低字线驱动电路中单器件端口压降, 解决了字线驱动电路的耐压与高压切换问题。仿真结果表明, 该电路可将频率为100 MHz的1.2 V低压域输入信号转化为高压域输出电压, 单条高速字线驱动电路的输出电压范围可达-10 V至10 V, 本征延时为1.4 ns; 负载为5 pF时, 传输延时为8.9 ns。

Abstract

In non-volatile compute-in-memory (CIM) chips, the gate equivalent capacitance of large-scale array and the equivalent capacitance of long-distance transmission line severely restricted the switching speed of word line drive circuit (WLDC). The different voltage of multi-voltage range required by the nonvolatile CIM device was much larger than the withstand voltage of single transistor in the WLDC. Therefore, this paper proposed a high speed WLDC for CIM. By combining with the working principle of array, a multi-stage pre-processing voltage control method was adopted to transmit a variety of high voltages in multiple voltage domains in a selective hierarchical manner, which could greatly reduce the propagation delay. In addition, a clamp voltage divider structure was adopted to reduce the voltage drop of single device in the WLDC, which could solve the voltage withstand and high voltage switching problems of the WLDC. Simulation results showed that the circuit could convert the 1.2 V input of 100 MHz frequency into the high voltage output. The range of a single high speed WLDC output voltage could reach -10 V to 10 V, and the intrinsic delay was 1.4 ns. When the load was 5 pF, the transmission delay was 8.9 ns.

参考文献

[1] HUANG X H, LIU C S, JIANG Y G, et al. In-memory computing to break the memory wall ［J］. Chinese Phys B, 2020, 29(7): 28-48.

[2] MONGA K, CHATURVEDI N, GURUNARAYANAN S. Dual-mode in-memory computing unit using spin hall-assisted MRAM for data-intensive applications ［J］. IEEE Trans Mag, 2021, 57(4): 1-10.

[3] HUNG J M, LI X Q, WU J J, et al. Challenges and trends in developing nonvolatile memory-enabled computing chips for intelligent edge devices ［J］. IEEE Trans Elec Dev, 2020, 67(4): 1444-1453.

[4] YANTIR H E, ELTAWIL A M, SALAMA L N. IMCA: an efficient in-memory convolution accelerator ［J］. IEEE Trans VLSI Syst, 2021, 29(3): 447-460.

[5] PAVAN P, BEZ R, OLIVO P, et al. Flash memory cells - an overview ［J］. Proceed IEEE, 1997, 85(8): 1248-1271.

[6] SINANGIL M E, ERBAGCI B, NAOUS R, et al. A 7-nm compute-in-memory SRAM macro supporting multi-bit input, weight and output and achieving 351 TOPS/W and 372.4 GOPS ［J］. IEEE J Sol Sta Circ, 2021, 56(1): 188-198.

[7] ZHANG S, HUANG K J, SHEN H B. A robust 8-bit non-volatile computing-in-memory core for low-power parallel MAC operations ［J］. IEEE Trans Circ Syst I: Regul Pap, 2020, 67(6): 1867-1880.

[8] LIU Z Y, REN E X, QIAO F, et al. NS-CIM: a current-mode computation-in-memory architecture enabling near-sensor processing for intelligent IoT vision nodes ［J］. IEEE Trans Circ Syst I: Regu Pap, 2020, 67(9): 2909-2922.

[9] GARCIA-MONTESDEOCA J C, MONTIEL-NELSON J A, NOOSHABADI S. High performance bootstrapped CMOS dual supply level shifter for 0.5 V input and 1 V output ［C］ // IEEE 12th Euro Conf Dig Syst Des. Patras, Greece. 2009: 311-314.

[10] MAGHSOUDLOO E, REZAEI M, SAWAN M, et al. A power-efficient wide-range signal level-shifter ［C］ // IEEE 13th Int NEWCAS. Grenoble, France. 2015: 1-4.

[11] 陈桂林, 马胜, 郭阳. 硬件加速神经网络综述［J］. 计算机研究与发展, 2019, 56(2): 240-253.

[12] 王佳妮, 周泽坤, 李颂, 等. 一种低功耗高稳态电平位移电路［J］. 微电子学, 2020, 50(3): 325-320.

[13] HASANBEGOVIC A, AUNET S. Low-power subthreshold to above threshold level shifter in 90 nm process ［C］ // NORCHIP. Trondheim, Norway. 2009: 1-4.

[14] KO J, YANG Y, KIM J, et al. Variation-tolerant WL driving scheme for high-capacity NAND flash memory ［J］. IEEE Trans VLSI Syst, 2019, 27(8): 1828-1839.

王雨桐, 虞致国, 车饶, 顾晓峰. 一种面向存算的高速字线驱动电路[J]. 微电子学, 2022, 52(1): 47. WANG Yutong, YU Zhiguo, CHE Rao, GU Xiaofeng. A High Speed Word Line Drive Circuit for Compute-in-Memory[J]. Microelectronics, 2022, 52(1): 47.

一种面向存算的高速字线驱动电路

关于本站 Cookie 的使用提示

全站搜索

一种面向存算的高速字线驱动电路

相关论文

相关资讯

关于本站 Cookie 的使用提示

全站搜索