一种超低功耗小面积的Σ-Δ ADC数字抽取滤波器

提出并实现了一种针对音频信号Σ-Δ模数转换器的超低功耗和低资源占用的数字抽取滤波器。该滤波器采用多级级联结构,由级联积分梳状滤波器、极简结构补偿器和全通多相型IIR滤波器组成,相较于传统FIR滤波器级联方案,能够以极低的阶数和硬件复杂度实现高倍抽取、极小的通带波纹和高水平的阻带衰减,同时具有近似线性相位特性。整体有效带宽为20 kHz,共完成128倍抽取。采用0.18 μm CMOS工艺完成ASIC设计,数字版图面积为0.37 mm2,功耗为125 μW,信噪比达到98.79 dB,有效位数为16 bit。与传统FIR结构抽取滤波器相比, 面积减小了60%, 功耗降低了20%。

Abstract

This research presented a digital decimation filter with ultra-low power and small area in the audio signal Σ-Δ analog-to-digital converters. The filter consisted of the cascaded integrating comb filter, the low order compensator, and the all-pass polyphase IIR filter. Compared with the conventional FIR filter, it contained lower orders and hardware complexity. Meanwhile, it could achieve high decimation, ultra-low passband ripple, high stopband attenuation and approximately linear phase. The overall effective bandwidth was 20 kHz, and the decimation factor was 128. The ASIC design was implemented in a 0.18 μm CMOS process. The digital layout area was 0.37 mm2, and the power was 125 μW. The SNR reached 98.79 dB, and the effective accuracy achieved 16 bit. Compared with that of the decimation filter of traditional FIR structure, the area of the proposed digital decimation filter was reduced by 60% and the power consumption was cut down by 20%.

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申泽生, 刘云涛, 方硕, 王云. 一种超低功耗小面积的Σ-Δ ADC数字抽取滤波器[J]. 微电子学, 2022, 52(4): 555. SHEN Zesheng, LIU Yuntao, FANG Shuo, WANG Yun. A Digital Decimation Filter ofΣ-Δ ADC with Ultra-Low Power and Small Area[J]. Microelectronics, 2022, 52(4): 555.

一种超低功耗小面积的Σ-Δ ADC数字抽取滤波器

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