目前已有一些在ESD和电磁干扰下存储器行为的表征研究, 但对静态随机存取存储器(SRAM)的连续波抗扰度的频率响应特性的研究很少。文章研究了SRAM在射频电磁干扰下的失效行为与机理。对SRAM芯片进行射频干扰测试发现, SRAM失效行为与其工作模式相关。使用Hspice进行晶体管级仿真。结果表明, SRAM处于数据保持时, 抗扰能力很强, 处于读写模式时, 抗扰能力较弱。进一步研究失效机理发现, 电源端干扰会导致路径延时的漂移和抖动, 造成SRAM读写失效。该研究可为存储器或系统级芯片的可靠性设计提供指导。

The failure behaviors of memory chips under ESD and electromagnetic interference (EMI) have been characterized by many researches, whereas the frequency response characteristics of continuous wave immunity of SRAM has not been researched yet. The failure behavior and mechanism of SRAM under RF EMI (RFI) was studied in this paper. The SRAM chips RFI testing results revealed that SRAM failure behavior was related to its operating state. Transistor-level simulation was carried out by Hspice. Results showed that the SRAM was highly immune to interference within data hold and weakly immune to interference within read/write state. Further study on the failure mechanism revealed that power-side disturbances caused drift and jitter in the path delay, resulting in SRAM read and write failure. This study could provide guidance for the reliability design of memory or system on chip.