分析了流水线A/D转换器采样电容与反馈电容之间的增益失配,探究了运放有限增益与流水线残差输出及A/D转换器输出的关系,建立了精确的系统模型。通过建立14位流水线A/D转换器Verilog-A的行为级模型,在数字域对流水线A/D转换器输出数字码进行分段平移。在第一级级间增益误差达到±0.012 5时,校正前信噪比仅为62 dB,校正后信噪比提升到85 dB。提出的校正方法可有效补偿由流水线级间增益导致的数字输出不连续和线性度下降。

The gain mismatch between sampling capacitance and feedback capacitance in pipeline A/D converters was analyzed. The relationship between the finite gain of operational amplifier and pipeline residual output, as well as the output of A/D converter, was investigated. So an accurate system model was established. Based on the Verilog-A behavioral model of 14 bit pipelined ADC, the digital output of pipelined ADC was shifted piecewisely in digital domain. When the inter-stage gain error of first stage reached ±0.012 5, the SNR was only 62 dB before calibration, and it was 85 dB after calibration. The proposed calibration method could compensate for the discontinuity of digital output and the linearity degeneration caused by inter-stage gain errors.