采用65 nm CMOS工艺,设计了一种宽带低相噪低杂散的Σ-Δ小数分频频率综合器。该频率综合器采用3个压控振荡器以及可编程分频链路实现宽带输出,每个压控振荡器采用自适应衬底偏置技术以减小PVT变化的影响。可编程分频器采用重定时单元同步输出,降低了分频器的相位噪声。自动频率校准模块采用一个可对压控振荡器直接计数的结构,缩短了频率锁定时间。Σ-Δ调制器中采用了陷波滤波结构,降低了高频量化噪声。后仿真结果表明,1.2 V电源电压下,该频率综合器可输出正交信号的频率范围为0.2~6 GHz,输出频率为3.762 5 GHz时,相位噪声为-113.59 dBc/Hz @1 MHz,参考杂散为-59.3 dBc,功耗为91 mW。

A Σ-Δ fractional-N frequency synthesizer with broadband, low phase noise and low spurious was designed in a 65 nm CMOS process. Three voltage-controlled oscillators and a programmable frequency division link was adopted in the frequency synthesizer to achieve broadband output, and each voltage-controlled oscillator introduced an adaptive body-biasing technique to reduce the impact of PVT changes. A retiming unit was taken in the programmable frequency divider to synchronize the output, which improved the phase noise of the frequency divider. The automatic frequency calibration circuit adopted a structure that directly counted the voltage-controlled oscillator, which shortened the frequency lock time. A notch filter structure was added to the Σ-Δ modulator to reduce output quantization noise. The post simulation results showed that the frequency range of the quadrature signal that the frequency synthesizer could output was 0.2 ~ 6 GHz under 1.2 V power supply voltage. When the output frequency was 3.762 5 GHz, the phase noise was -113.59 dBc/Hz @1 MHz, the reference spurious was -59.3 dBc, and the power consumption was 91 mW.